Lines Matching +full:4 +full:- +full:16
1 /* SPDX-License-Identifier: GPL-2.0-only */
11 #include <dt-bindings/memory/mtk-memory-port.h>
14 * MM IOMMU supports 16GB dma address. We separate it to four ranges:
15 * 0 ~ 4G; 4G ~ 8G; 8G ~ 12G; 12G ~ 16G, we could adjust these masters
18 * b) The iova of any master can NOT cross the 4G/8G/12G boundary.
22 * modules dma-address-region larbs-ports
23 * disp 0 ~ 4G larb0/1/2
24 * vcodec 4G ~ 8G larb4/7
26 * N/A 12G ~ 16G
28 * CCU1 0x24400_0000 ~ 0x247ff_ffff larb14: port 4/5
32 /* LARB 0 -- MMSYS */
38 /* LARB 1 -- MMSYS */
43 #define IOMMU_PORT_L1_DISP_FAKE1 MTK_M4U_ID(1, 4)
45 /* LARB 2 -- MMSYS */
50 #define IOMMU_PORT_L2_DISP_FAKE0 MTK_M4U_ID(2, 4)
52 /* LARB 4 -- VDEC */
53 #define IOMMU_PORT_L4_HW_VDEC_MC_EXT MTK_M4U_ID(4, 0)
54 #define IOMMU_PORT_L4_HW_VDEC_UFO_EXT MTK_M4U_ID(4, 1)
55 #define IOMMU_PORT_L4_HW_VDEC_PP_EXT MTK_M4U_ID(4, 2)
56 #define IOMMU_PORT_L4_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(4, 3)
57 #define IOMMU_PORT_L4_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(4, 4)
58 #define IOMMU_PORT_L4_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(4, 5)
59 #define IOMMU_PORT_L4_HW_VDEC_TILE_EXT MTK_M4U_ID(4, 6)
60 #define IOMMU_PORT_L4_HW_VDEC_VLD_EXT MTK_M4U_ID(4, 7)
61 #define IOMMU_PORT_L4_HW_VDEC_VLD2_EXT MTK_M4U_ID(4, 8)
62 #define IOMMU_PORT_L4_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(4, 9)
63 #define IOMMU_PORT_L4_HW_VDEC_UFO_ENC_EXT MTK_M4U_ID(4, 10)
64 #define IOMMU_PORT_L4_HW_VDEC_RG_CTRL_DMA_EXT MTK_M4U_ID(4, 11)
65 #define IOMMU_PORT_L4_HW_MINI_MDP_R0_EXT MTK_M4U_ID(4, 12)
66 #define IOMMU_PORT_L4_HW_MINI_MDP_W0_EXT MTK_M4U_ID(4, 13)
68 /* LARB 7 -- VENC */
73 #define IOMMU_PORT_L7_VENC_RD_COMV MTK_M4U_ID(7, 4)
83 /* LARB 8 -- WPE */
88 /* LARB 9 -- IMG-1 */
93 #define IOMMU_PORT_L9_IMG_LCE_D1 MTK_M4U_ID(9, 4)
105 #define IOMMU_PORT_L9_IMG_WPE_RDMA0 MTK_M4U_ID(9, 16)
119 /* LARB 11 -- IMG-2 */
124 #define IOMMU_PORT_L11_IMG_LCE_D1 MTK_M4U_ID(11, 4)
136 #define IOMMU_PORT_L11_IMG_WPE_RDMA0 MTK_M4U_ID(11, 16)
150 /* LARB 13 -- CAM */
161 /* LARB 14 -- CAM */
162 #define IOMMU_PORT_L14_CAM_CCUI MTK_M4U_ID(14, 4)
165 /* LARB 16 -- RAW-A */
166 #define IOMMU_PORT_L16_CAM_IMGO_R1_A MTK_M4U_ID(16, 0)
167 #define IOMMU_PORT_L16_CAM_RRZO_R1_A MTK_M4U_ID(16, 1)
168 #define IOMMU_PORT_L16_CAM_CQI_R1_A MTK_M4U_ID(16, 2)
169 #define IOMMU_PORT_L16_CAM_BPCI_R1_A MTK_M4U_ID(16, 3)
170 #define IOMMU_PORT_L16_CAM_YUVO_R1_A MTK_M4U_ID(16, 4)
171 #define IOMMU_PORT_L16_CAM_UFDI_R2_A MTK_M4U_ID(16, 5)
172 #define IOMMU_PORT_L16_CAM_RAWI_R2_A MTK_M4U_ID(16, 6)
173 #define IOMMU_PORT_L16_CAM_RAWI_R3_A MTK_M4U_ID(16, 7)
174 #define IOMMU_PORT_L16_CAM_AAO_R1_A MTK_M4U_ID(16, 8)
175 #define IOMMU_PORT_L16_CAM_AFO_R1_A MTK_M4U_ID(16, 9)
176 #define IOMMU_PORT_L16_CAM_FLKO_R1_A MTK_M4U_ID(16, 10)
177 #define IOMMU_PORT_L16_CAM_LCESO_R1_A MTK_M4U_ID(16, 11)
178 #define IOMMU_PORT_L16_CAM_CRZO_R1_A MTK_M4U_ID(16, 12)
179 #define IOMMU_PORT_L16_CAM_LTMSO_R1_A MTK_M4U_ID(16, 13)
180 #define IOMMU_PORT_L16_CAM_RSSO_R1_A MTK_M4U_ID(16, 14)
181 #define IOMMU_PORT_L16_CAM_AAHO_R1_A MTK_M4U_ID(16, 15)
182 #define IOMMU_PORT_L16_CAM_LSCI_R1_A MTK_M4U_ID(16, 16)
184 /* LARB 17 -- RAW-B */
189 #define IOMMU_PORT_L17_CAM_YUVO_R1_B MTK_M4U_ID(17, 4)
201 #define IOMMU_PORT_L17_CAM_LSCI_R1_B MTK_M4U_ID(17, 16)
203 /* LARB 19 -- IPE */
209 /* LARB 20 -- IPE */
214 #define IOMMU_PORT_L20_IPE_RSC_RDMA0 MTK_M4U_ID(20, 4)