Lines Matching refs:M4U_LARB0_ID
12 #define M4U_LARB0_ID 0 macro
19 #define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0)
20 #define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 1)
21 #define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB0_ID, 2)
22 #define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 3)
23 #define M4U_PORT_DISP_OVL1 MTK_M4U_ID(M4U_LARB0_ID, 4)
24 #define M4U_PORT_DISP_RDMA2 MTK_M4U_ID(M4U_LARB0_ID, 5)
25 #define M4U_PORT_DISP_WDMA1 MTK_M4U_ID(M4U_LARB0_ID, 6)
26 #define M4U_PORT_DISP_OD_R MTK_M4U_ID(M4U_LARB0_ID, 7)
27 #define M4U_PORT_DISP_OD_W MTK_M4U_ID(M4U_LARB0_ID, 8)
28 #define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 9)
29 #define M4U_PORT_MDP_RDMA1 MTK_M4U_ID(M4U_LARB0_ID, 10)
30 #define M4U_PORT_MDP_WDMA MTK_M4U_ID(M4U_LARB0_ID, 11)
31 #define M4U_PORT_MDP_WROT0 MTK_M4U_ID(M4U_LARB0_ID, 12)
32 #define M4U_PORT_MDP_WROT1 MTK_M4U_ID(M4U_LARB0_ID, 13)