dt-bindings/clock/tegra234-clock.h

81 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_AXI_CLK_0 divider gated output */
83 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0 divider gated output */
87 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK divider gated output */
242 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SE switch divider gated output */
617 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SEU1 switch divider gated output */
675 /** @brief GBE_UPHY_MGBES_APP_CLK switch divider gated output */
691 /** @brief GBE_UPHY_MGBE0_TX_CLK divider gated output */
693 /** @brief GBE_UPHY_MGBE0_TX_PCS_CLK divider gated output */
705 /** @brief GBE_UPHY_MGBE0_PTP_REF_CLK divider gated output */
709 /** @brief GBE_UPHY_MGBE1_TX_CLK divider gated output */
711 /** @brief GBE_UPHY_MGBE1_TX_PCS_CLK divider gated output */
723 /** @brief GBE_UPHY_MGBE1_PTP_REF_CLK divider gated output */
727 /** @brief GBE_UPHY_MGBE2_TX_CLK divider gated output */
729 /** @brief GBE_UPHY_MGBE2_TX_PCS_CLK divider gated output */
741 /** @brief GBE_UPHY_MGBE2_PTP_REF_CLK divider gated output */
745 /** @brief GBE_UPHY_MGBE3_TX_CLK divider gated output */
747 /** @brief GBE_UPHY_MGBE3_TX_PCS_CLK divider gated output */
759 /** @brief GBE_UPHY_MGBE3_PTP_REF_CLK divider gated output */