dt-bindings/clock/tegra234-clock.h

1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */
382 /** @brief NAFLL clock source for BPMP */
470 /** @brief RX clock recovered from MGBE0 lane input */
472 /** @brief RX clock recovered from MGBE1 lane input */
474 /** @brief RX clock recovered from MGBE2 lane input */
476 /** @brief RX clock recovered from MGBE3 lane input */
518 /** @brief NAFLL clock source for CPU cluster 0 */
521 /** @brief NAFLL clock source for CPU cluster 1 */
524 /** @brief NAFLL clock source for CPU cluster 2 */
657 /** @brief Monitored branch of MBGE0 RX input clock */
659 /** @brief Monitored branch of MBGE1 RX input clock */
661 /** @brief Monitored branch of MBGE2 RX input clock */
663 /** @brief Monitored branch of MBGE3 RX input clock */
665 /** @brief Monitored branch of MGBE0 RX PCS mux output */
667 /** @brief Monitored branch of MGBE1 RX PCS mux output */
669 /** @brief Monitored branch of MGBE2 RX PCS mux output */
671 /** @brief Monitored branch of MGBE3 RX PCS mux output */
681 /** @brief RX PCS clock recovered from MGBE0 lane input */
683 /** @brief RX PCS clock recovered from MGBE1 lane input */
685 /** @brief RX PCS clock recovered from MGBE2 lane input */
687 /** @brief RX PCS clock recovered from MGBE3 lane input */
801 /** @brief NAFLL clock source for CPU cluster 0 DSUCLK */
804 /** @brief NAFLL clock source for CPU cluster 1 DSUCLK */
807 /** @brief NAFLL clock source for CPU cluster 2 DSUCLK */