Lines Matching +full:25 +full:- +full:18
1 /* SPDX-License-Identifier: GPL-2.0 */
22 #define CLK_MOUT_ACLK_CAM1_552_B 18
29 #define CLK_MOUT_ACLK_GSCL_333 25
219 #define CLK_MOUT_CLK2X_PHY_C 18
226 #define CLK_MOUT_ACLK_MIFNM_400 25
413 #define CLK_PCLK_I2C0 18
420 #define CLK_PCLK_HSI2C7 25
483 #define CLK_PCLK_TZPC8 18
490 #define CLK_PCLK_TZPC1 25
526 #define CLK_MOUT_PHYCLK_UFS_RX1_SYMBOL_USER 18
533 #define CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY 25
634 #define CLK_PCLK_SMMU_MDMA1 18
641 #define CLK_PCLK_G2D 25
663 #define CLK_MOUT_SCLK_DECON_TV_ECLK 18
670 #define CLK_MOUT_SCLK_DECON_TV_VCLK_A_DISP 25
780 #define CLK_ACLK_AXIDS0_LPASSP 18
787 #define CLK_PCLK_WDT1 25
845 #define CLK_PCLK_SYSREG_G3D 18
867 #define CLK_PCLK_BTS_GSCL2 18
874 #define CLK_PCLK_GSCL0 25
900 #define CLK_ACLK_ASATBSLV_APOLLO_3_CSSYS 18
907 #define CLK_PCLK_ASAPBMST_CSSYS_APOLLO 25
935 #define CLK_ACLK_ATB_APOLLO0_CSSYS 18
942 #define CLK_PCLK_ASYNCAPB_ISP_CSSYS 25
978 #define CLK_PCLK_BTS_JPEG 18
985 #define CLK_PCLK_M2MSCALER0 25
1011 #define CLK_PCLK_SMMU_MFC_0 18
1033 #define CLK_PCLK_SMMU_HEVC_0 18
1055 #define CLK_ACLK_ASYNCAHBM_ISP1P 18
1062 #define CLK_ACLK_AHB2APB_ISP2P 25
1135 #define CLK_MOUT_ACLK_CSIS0_A 18
1142 #define CLK_MOUT_SCLK_LITE_FREECNT_A 25
1272 #define CLK_DIV_PCLK_DBG_CAM1 18
1280 #define CLK_ACLK_ISP_GIC 25