Lines Matching full:exynos4x12
29 #define CLK_MOUT_MPLL_USER_T 17 /* Exynos4x12 only */
30 #define CLK_MOUT_MPLL_USER_C 18 /* Exynos4x12 only */
86 #define CLK_SCLK_PWM_ISP 173 /* Exynos4x12 only */
87 #define CLK_SCLK_SPI0_ISP 174 /* Exynos4x12 only */
88 #define CLK_SCLK_SPI1_ISP 175 /* Exynos4x12 only */
89 #define CLK_SCLK_UART_ISP 176 /* Exynos4x12 only */
190 #define CLK_ASYNC_G3D 353 /* Exynos4x12 only */
191 #define CLK_PWM_ISP_SCLK 379 /* Exynos4x12 only */
192 #define CLK_SPI0_ISP_SCLK 380 /* Exynos4x12 only */
193 #define CLK_SPI1_ISP_SCLK 381 /* Exynos4x12 only */
194 #define CLK_UART_ISP_SCLK 382 /* Exynos4x12 only */
209 #define CLK_ACLK400_MCUISP 395 /* Exynos4x12 only */
233 #define CLK_DIV_ACLK200 454 /* Exynos4x12 only */
234 #define CLK_DIV_ACLK400_MCUISP 455 /* Exynos4x12 only */
237 #define CLK_DIV_C2C 458 /* Exynos4x12 only */
242 /* Exynos4x12 ISP clocks */