46 static int wdt_cfg_enter = 0x87;/* key to unlock configuration space */
47 static int wdt_cfg_leave = 0xAA;/* key to lock configuration space */
55 module_param(timeout, int, 0);
61 module_param(nowayout, bool, 0);
67 module_param(early_disable, int, 0);
68 MODULE_PARM_DESC(early_disable, "Disable watchdog at boot time (default=0)");
74 #define WDT_EFER (wdt_io+0)   /* Extended Function Enable Registers */
75 #define WDT_EFIR (wdt_io+0)   /* Extended Function Index Register
79 #define W83627HF_LD_WDT		0x08
81 #define W83627HF_ID		0x52
82 #define W83627S_ID		0x59
83 #define W83697HF_ID		0x60
84 #define W83697UG_ID		0x68
85 #define W83637HF_ID		0x70
86 #define W83627THF_ID		0x82
87 #define W83687THF_ID		0x85
88 #define W83627EHF_ID		0x88
89 #define W83627DHG_ID		0xa0
90 #define W83627UHG_ID		0xa2
91 #define W83667HG_ID		0xa5
92 #define W83627DHG_P_ID		0xb0
93 #define W83667HG_B_ID		0xb3
94 #define NCT6775_ID		0xb4
95 #define NCT6776_ID		0xc3
96 #define NCT6102_ID		0xc4
97 #define NCT6116_ID		0xd2
98 #define NCT6779_ID		0xc5
99 #define NCT6791_ID		0xc8
100 #define NCT6792_ID		0xc9
101 #define NCT6793_ID		0xd1
102 #define NCT6795_ID		0xd3
103 #define NCT6796_ID		0xd4	/* also NCT9697D, NCT9698D */
105 #define W83627HF_WDT_TIMEOUT	0xf6
106 #define W83697HF_WDT_TIMEOUT	0xf4
107 #define NCT6102D_WDT_TIMEOUT	0xf1
109 #define W83627HF_WDT_CONTROL	0xf5
110 #define W83697HF_WDT_CONTROL	0xf3
111 #define NCT6102D_WDT_CONTROL	0xf0
113 #define W836X7HF_WDT_CSR	0xf7
114 #define NCT6102D_WDT_CSR	0xf2
116 #define WDT_CSR_STATUS		0x10
117 #define WDT_CSR_KBD		0x40
118 #define WDT_CSR_MOUSE		0x80
140 	return 0;  in superio_enter()
145 	superio_outb(0x07, ld);  in superio_select()
165 	/* set CR30 bit 0 to activate GPIO2 */  in w83627hf_init()
166 	t = superio_inb(0x30);  in w83627hf_init()
167 	if (!(t & 0x01))  in w83627hf_init()
168 		superio_outb(0x30, t | 0x01);  in w83627hf_init()
173 		t = superio_inb(0x2B) & ~0x10;  in w83627hf_init()
174 		superio_outb(0x2B, t); /* set GPIO24 to WDT0 */  in w83627hf_init()
178 		t = superio_inb(0x29) & ~0x60;  in w83627hf_init()
179 		t |= 0x20;  in w83627hf_init()
180 		superio_outb(0x29, t);  in w83627hf_init()
184 		t = superio_inb(0x2b) & ~0x04;  in w83627hf_init()
185 		superio_outb(0x2b, t);  in w83627hf_init()
188 		t = (superio_inb(0x2B) & ~0x08) | 0x04;  in w83627hf_init()
189 		superio_outb(0x2B, t); /* set GPIO3 to WDT0 */  in w83627hf_init()
193 		t = superio_inb(0x2D) & ~0x01; /* PIN77 -> WDT0# */  in w83627hf_init()
194 		superio_outb(0x2D, t); /* set GPIO5 to WDT0 */  in w83627hf_init()
196 		t |= 0x02;	/* enable the WDTO# output low pulse  in w83627hf_init()
203 		t = superio_inb(0x2C) & ~0x80; /* PIN47 -> WDT0# */  in w83627hf_init()
204 		superio_outb(0x2C, t);  in w83627hf_init()
227 		t |= 0x02;	/* enable the WDTO# output low pulse  in w83627hf_init()
236 	if (t != 0) {  in w83627hf_init()
239 			superio_outb(cr_wdt_timeout, 0);  in w83627hf_init()
248 	t = superio_inb(cr_wdt_control) & ~0x0C;  in w83627hf_init()
261 	return 0;  in w83627hf_init()
276 	return 0;  in wdt_set_time()
286 	return wdt_set_time(0);  in wdt_stop()
293 	return 0;  in wdt_set_timeout()
303 		return 0;  in wdt_get_time()
355 	val = superio_inb(0x20);  in wdt_find()
436 	case 0xff:  in wdt_find()
441 		pr_err("Unsupported chip ID: 0x%02x\n", val);  in wdt_find()
455 	wdt_cfg_enter = 0x88;  in wdt_use_alt_key()
456 	wdt_cfg_leave = 0xBB;  in wdt_use_alt_key()
458 	return 0;  in wdt_use_alt_key()
507 	wdt_io = 0x2e;  in wdt_init()
508 	chip = wdt_find(0x2e);  in wdt_init()
509 	if (chip < 0) {  in wdt_init()
510 		wdt_io = 0x4e;  in wdt_init()
511 		chip = wdt_find(0x4e);  in wdt_init()
512 		if (chip < 0)  in wdt_init()