1 // SPDX-License-Identifier: GPL-2.0-only
10  * - Base prescale of (2 << 25), providing tick duration T_0: 168ms @ 200MHz
11  * - PRESCALE: logarithmic prescaler adding a factor of {1, 2, 4, 8}
12  * - Phase 1: Times out after (PHASE1 + 1) × PRESCALE × T_0
13  *   Generates an interrupt, WDT cannot be stopped after phase 1
14  * - Phase 2: starts after phase 1, times out after (PHASE2 + 1) × PRESCALE × T_0
79 	v = ioread32(ctrl->base + OTTO_WDT_REG_CTRL);  in otto_wdt_start()
81 	iowrite32(v, ctrl->base + OTTO_WDT_REG_CTRL);  in otto_wdt_start()
91 	v = ioread32(ctrl->base + OTTO_WDT_REG_CTRL);  in otto_wdt_stop()
93 	iowrite32(v, ctrl->base + OTTO_WDT_REG_CTRL);  in otto_wdt_stop()
102 	iowrite32(OTTO_WDT_CNTR_PING, ctrl->base + OTTO_WDT_REG_CNTR);  in otto_wdt_ping()
109 	return DIV_ROUND_CLOSEST(1 << (25 + prescale), ctrl->clk_rate_khz);  in otto_wdt_tick_ms()
140 			return -EINVAL;  in otto_wdt_determine_timeouts()
144 		phase1_ticks = div_round_ticks(timeout_ms - pretimeout_ms, tick_ms, 1);  in otto_wdt_determine_timeouts()
145 		phase2_ticks = total_ticks - phase1_ticks;  in otto_wdt_determine_timeouts()
151 	v = ioread32(ctrl->base + OTTO_WDT_REG_CTRL);  in otto_wdt_determine_timeouts()
154 	v |= FIELD_PREP(OTTO_WDT_CTRL_PHASE1, phase1_ticks - 1);  in otto_wdt_determine_timeouts()
155 	v |= FIELD_PREP(OTTO_WDT_CTRL_PHASE2, phase2_ticks - 1);  in otto_wdt_determine_timeouts()
158 	iowrite32(v, ctrl->base + OTTO_WDT_REG_CTRL);  in otto_wdt_determine_timeouts()
161 	ctrl->wdev.timeout = timeout_ms / 1000;  in otto_wdt_determine_timeouts()
164 	ctrl->wdev.pretimeout = pretimeout_ms / 1000;  in otto_wdt_determine_timeouts()
171 	return otto_wdt_determine_timeouts(wdev, val, min(wdev->pretimeout, val - 1));  in otto_wdt_set_timeout()
176 	return otto_wdt_determine_timeouts(wdev, wdev->timeout, val);  in otto_wdt_set_pretimeout()
186 	disable_irq(ctrl->irq_phase1);  in otto_wdt_restart()
202 	iowrite32(v, ctrl->base + OTTO_WDT_REG_CTRL);  in otto_wdt_restart()
213 	iowrite32(OTTO_WDT_INTR_PHASE_1, ctrl->base + OTTO_WDT_REG_INTR);  in otto_wdt_phase1_isr()
214 	dev_crit(ctrl->dev, "phase 1 timeout\n");  in otto_wdt_phase1_isr()
215 	watchdog_notify_pretimeout(&ctrl->wdev);  in otto_wdt_phase1_isr()
242 	clk = devm_clk_get_enabled(ctrl->dev, NULL);  in otto_wdt_probe_clk()
244 		return dev_err_probe(ctrl->dev, PTR_ERR(clk), "Failed to get clock\n");  in otto_wdt_probe_clk()
246 	ctrl->clk_rate_khz = clk_get_rate(clk) / 1000;  in otto_wdt_probe_clk()
247 	if (ctrl->clk_rate_khz == 0)  in otto_wdt_probe_clk()
248 		return dev_err_probe(ctrl->dev, -ENXIO, "Failed to get clock rate\n");  in otto_wdt_probe_clk()
255 	static const char *mode_property = "realtek,reset-mode";  in otto_wdt_probe_reset_mode()
256 	const struct fwnode_handle *node = ctrl->dev->fwnode;  in otto_wdt_probe_reset_mode()
262 		return -ENXIO;  in otto_wdt_probe_reset_mode()
270 		return -EINVAL;  in otto_wdt_probe_reset_mode()
279 		return -EINVAL;  in otto_wdt_probe_reset_mode()
281 	v = ioread32(ctrl->base + OTTO_WDT_REG_CTRL);  in otto_wdt_probe_reset_mode()
284 	iowrite32(v, ctrl->base + OTTO_WDT_REG_CTRL);  in otto_wdt_probe_reset_mode()
291 	struct device *dev = &pdev->dev;  in otto_wdt_probe()
298 		return -ENOMEM;  in otto_wdt_probe()
300 	ctrl->dev = dev;  in otto_wdt_probe()
301 	ctrl->base = devm_platform_ioremap_resource(pdev, 0);  in otto_wdt_probe()
302 	if (IS_ERR(ctrl->base))  in otto_wdt_probe()
303 		return PTR_ERR(ctrl->base);  in otto_wdt_probe()
307 			ctrl->base + OTTO_WDT_REG_INTR);  in otto_wdt_probe()
308 	iowrite32(OTTO_WDT_CTRL_DEFAULT, ctrl->base + OTTO_WDT_REG_CTRL);  in otto_wdt_probe()
314 	ctrl->irq_phase1 = platform_get_irq_byname(pdev, "phase1");  in otto_wdt_probe()
315 	if (ctrl->irq_phase1 < 0)  in otto_wdt_probe()
316 		return ctrl->irq_phase1;  in otto_wdt_probe()
318 	ret = devm_request_irq(dev, ctrl->irq_phase1, otto_wdt_phase1_isr, 0,  in otto_wdt_probe()
319 			"realtek-otto-wdt", ctrl);  in otto_wdt_probe()
327 	ctrl->wdev.parent = dev;  in otto_wdt_probe()
328 	ctrl->wdev.info = &otto_wdt_info;  in otto_wdt_probe()
329 	ctrl->wdev.ops = &otto_wdt_ops;  in otto_wdt_probe()
335 	ctrl->wdev.min_timeout = 2;  in otto_wdt_probe()
337 	ctrl->wdev.max_hw_heartbeat_ms = max_tick_ms * OTTO_WDT_TIMEOUT_TICKS_MAX;  in otto_wdt_probe()
338 	ctrl->wdev.timeout = min(30U, ctrl->wdev.max_hw_heartbeat_ms / 1000);  in otto_wdt_probe()
340 	watchdog_set_drvdata(&ctrl->wdev, ctrl);  in otto_wdt_probe()
341 	watchdog_init_timeout(&ctrl->wdev, 0, dev);  in otto_wdt_probe()
342 	watchdog_stop_on_reboot(&ctrl->wdev);  in otto_wdt_probe()
343 	watchdog_set_restart_priority(&ctrl->wdev, 128);  in otto_wdt_probe()
345 	ret = otto_wdt_determine_timeouts(&ctrl->wdev, ctrl->wdev.timeout, 1);  in otto_wdt_probe()
349 	return devm_watchdog_register_device(dev, &ctrl->wdev);  in otto_wdt_probe()
353 	{ .compatible = "realtek,rtl8380-wdt" },
354 	{ .compatible = "realtek,rtl8390-wdt" },
355 	{ .compatible = "realtek,rtl9300-wdt" },
356 	{ .compatible = "realtek,rtl9310-wdt" },
364 		.name = "realtek-otto-watchdog",