Lines Matching +full:timer +full:- +full:watchdog

1 // SPDX-License-Identifier: GPL-2.0-only
3 * PIKA FPGA based Watchdog Timer
19 #include <linux/watchdog.h>
22 #include <linux/timer.h>
29 #define DRV_NAME "PIKA-WDT"
34 /* Timer heartbeat (500ms) */
41 MODULE_PARM_DESC(heartbeat, "Watchdog heartbeats in seconds. "
46 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
51 unsigned long next_heartbeat; /* the next_heartbeat for the timer */
55 struct timer_list timer; /* The timer that pings the watchdog */ member
67 * Reload the watchdog timer. (ie, pat the watchdog)
71 /* -- FPGA: Reset Control Register (32bit R/W) (Offset: 0x14) -- in pikawdt_reset()
72 * Bit 7, WTCHDG_EN: When set to 1, the watchdog timer is enabled. in pikawdt_reset()
73 * Once enabled, it cannot be disabled. The watchdog can be in pikawdt_reset()
76 * Bit 8-11, WTCHDG_TIMEOUT_SEC: Sets the watchdog timeout value in in pikawdt_reset()
81 /* enable with max timeout - 15 seconds */ in pikawdt_reset()
87 * Timer tick
94 mod_timer(&pikawdt_private.timer, jiffies + WDT_TIMEOUT); in pikawdt_ping()
108 mod_timer(&pikawdt_private.timer, jiffies + WDT_TIMEOUT); in pikawdt_start()
112 * Watchdog device is opened, and watchdog starts running.
116 /* /dev/watchdog can only be opened once */ in pikawdt_open()
118 return -EBUSY; in pikawdt_open()
126 * Close the watchdog device.
132 del_timer(&pikawdt_private.timer); in pikawdt_release()
140 * Pat the watchdog whenever device is written to.
157 return -EFAULT; in pikawdt_write()
171 * Handle commands from user-space.
182 return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0; in pikawdt_ioctl()
196 return -EFAULT; in pikawdt_ioctl()
206 return -ENOTTY; in pikawdt_ioctl()
221 .name = "watchdog",
235 return -ENOENT; in pikawdt_init()
242 return -ENOMEM; in pikawdt_init()
248 np = of_find_compatible_node(NULL, NULL, "pika,fpga-sd"); in pikawdt_init()
250 pr_err("Unable to find fpga-sd\n"); in pikawdt_init()
251 ret = -ENOENT; in pikawdt_init()
258 pr_err("Unable to map fpga-sd\n"); in pikawdt_init()
259 ret = -ENOMEM; in pikawdt_init()
263 /* -- FPGA: POST Test Results Register 1 (32bit R/W) (Offset: 0x4040) -- in pikawdt_init()
264 * Bit 31, WDOG: Set to 1 when the last reset was caused by a watchdog in pikawdt_init()
273 timer_setup(&pikawdt_private.timer, pikawdt_ping, 0); in pikawdt_init()
301 MODULE_DESCRIPTION("PIKA FPGA based Watchdog Timer");