Lines Matching +full:timeout +full:- +full:enable
1 // SPDX-License-Identifier: GPL-2.0
78 return -ETIMEDOUT; in imx7ulp_wdt_wait_ulk()
86 u32 val = readl(wdt->base + WDOG_CS); in imx7ulp_wdt_wait_rcs()
87 u64 timeout = (val & WDOG_CS_PRES) ? in imx7ulp_wdt_wait_rcs() local
93 readl_poll_timeout(wdt->base + WDOG_CS, val, val & WDOG_CS_RCS, 100, in imx7ulp_wdt_wait_rcs()
94 timeout)) in imx7ulp_wdt_wait_rcs()
95 ret = -ETIMEDOUT; in imx7ulp_wdt_wait_rcs()
98 if (wdt->hw->post_rcs_wait) in imx7ulp_wdt_wait_rcs()
104 static int _imx7ulp_wdt_enable(struct imx7ulp_wdt_device *wdt, bool enable) in _imx7ulp_wdt_enable() argument
106 u32 val = readl(wdt->base + WDOG_CS); in _imx7ulp_wdt_enable()
110 writel(UNLOCK, wdt->base + WDOG_CNT); in _imx7ulp_wdt_enable()
111 ret = imx7ulp_wdt_wait_ulk(wdt->base); in _imx7ulp_wdt_enable()
114 if (enable) in _imx7ulp_wdt_enable()
115 writel(val | WDOG_CS_EN, wdt->base + WDOG_CS); in _imx7ulp_wdt_enable()
117 writel(val & ~WDOG_CS_EN, wdt->base + WDOG_CS); in _imx7ulp_wdt_enable()
129 static int imx7ulp_wdt_enable(struct watchdog_device *wdog, bool enable) in imx7ulp_wdt_enable() argument
137 ret = _imx7ulp_wdt_enable(wdt, enable); in imx7ulp_wdt_enable()
138 val = readl(wdt->base + WDOG_CS); in imx7ulp_wdt_enable()
139 } while (--loop > 0 && ((!!(val & WDOG_CS_EN)) != enable || ret)); in imx7ulp_wdt_enable()
142 return -EBUSY; in imx7ulp_wdt_enable()
151 writel(REFRESH, wdt->base + WDOG_CNT); in imx7ulp_wdt_ping()
172 writel(UNLOCK, wdt->base + WDOG_CNT); in _imx7ulp_wdt_set_timeout()
173 ret = imx7ulp_wdt_wait_ulk(wdt->base); in _imx7ulp_wdt_set_timeout()
176 writel(toval, wdt->base + WDOG_TOVAL); in _imx7ulp_wdt_set_timeout()
187 unsigned int timeout) in imx7ulp_wdt_set_timeout() argument
190 u32 toval = wdt->hw->wdog_clock_rate * timeout; in imx7ulp_wdt_set_timeout()
197 val = readl(wdt->base + WDOG_TOVAL); in imx7ulp_wdt_set_timeout()
198 } while (--loop > 0 && (val != toval || ret)); in imx7ulp_wdt_set_timeout()
201 return -EBUSY; in imx7ulp_wdt_set_timeout()
203 wdog->timeout = timeout; in imx7ulp_wdt_set_timeout()
217 ret = imx7ulp_wdt_set_timeout(&wdt->wdd, 1); in imx7ulp_wdt_restart()
243 static int _imx7ulp_wdt_init(struct imx7ulp_wdt_device *wdt, unsigned int timeout, unsigned int cs) in _imx7ulp_wdt_init() argument
250 val = readl(wdt->base + WDOG_CS); in _imx7ulp_wdt_init()
252 writel(UNLOCK, wdt->base + WDOG_CNT); in _imx7ulp_wdt_init()
256 writel_relaxed(UNLOCK_SEQ0, wdt->base + WDOG_CNT); in _imx7ulp_wdt_init()
257 writel_relaxed(UNLOCK_SEQ1, wdt->base + WDOG_CNT); in _imx7ulp_wdt_init()
261 ret = imx7ulp_wdt_wait_ulk(wdt->base); in _imx7ulp_wdt_init()
265 /* set an initial timeout value in TOVAL */ in _imx7ulp_wdt_init()
266 writel(timeout, wdt->base + WDOG_TOVAL); in _imx7ulp_wdt_init()
267 writel(cs, wdt->base + WDOG_CS); in _imx7ulp_wdt_init()
278 static int imx7ulp_wdt_init(struct imx7ulp_wdt_device *wdt, unsigned int timeout) in imx7ulp_wdt_init() argument
280 /* enable 32bit command sequence and reconfigure */ in imx7ulp_wdt_init()
287 if (wdt->hw->prescaler_enable) in imx7ulp_wdt_init()
290 if (wdt->ext_reset) in imx7ulp_wdt_init()
293 if (readl(wdt->base + WDOG_CS) & WDOG_CS_EN) { in imx7ulp_wdt_init()
294 set_bit(WDOG_HW_RUNNING, &wdt->wdd.status); in imx7ulp_wdt_init()
299 ret = _imx7ulp_wdt_init(wdt, timeout, val); in imx7ulp_wdt_init()
300 toval = readl(wdt->base + WDOG_TOVAL); in imx7ulp_wdt_init()
301 cs = readl(wdt->base + WDOG_CS); in imx7ulp_wdt_init()
303 } while (--loop > 0 && (cs != val || toval != timeout || ret)); in imx7ulp_wdt_init()
306 return -EBUSY; in imx7ulp_wdt_init()
314 struct device *dev = &pdev->dev; in imx7ulp_wdt_probe()
320 return -ENOMEM; in imx7ulp_wdt_probe()
324 imx7ulp_wdt->base = devm_platform_ioremap_resource(pdev, 0); in imx7ulp_wdt_probe()
325 if (IS_ERR(imx7ulp_wdt->base)) in imx7ulp_wdt_probe()
326 return PTR_ERR(imx7ulp_wdt->base); in imx7ulp_wdt_probe()
328 imx7ulp_wdt->clk = devm_clk_get_enabled(dev, NULL); in imx7ulp_wdt_probe()
329 if (IS_ERR(imx7ulp_wdt->clk)) { in imx7ulp_wdt_probe()
331 return PTR_ERR(imx7ulp_wdt->clk); in imx7ulp_wdt_probe()
335 imx7ulp_wdt->ext_reset = of_property_read_bool(dev->of_node, "fsl,ext-reset-output"); in imx7ulp_wdt_probe()
337 wdog = &imx7ulp_wdt->wdd; in imx7ulp_wdt_probe()
338 wdog->info = &imx7ulp_wdt_info; in imx7ulp_wdt_probe()
339 wdog->ops = &imx7ulp_wdt_ops; in imx7ulp_wdt_probe()
340 wdog->min_timeout = 1; in imx7ulp_wdt_probe()
341 wdog->max_timeout = MAX_TIMEOUT; in imx7ulp_wdt_probe()
342 wdog->parent = dev; in imx7ulp_wdt_probe()
343 wdog->timeout = DEFAULT_TIMEOUT; in imx7ulp_wdt_probe()
350 imx7ulp_wdt->hw = of_device_get_match_data(dev); in imx7ulp_wdt_probe()
351 ret = imx7ulp_wdt_init(imx7ulp_wdt, wdog->timeout * imx7ulp_wdt->hw->wdog_clock_rate); in imx7ulp_wdt_probe()
362 if (watchdog_active(&imx7ulp_wdt->wdd)) in imx7ulp_wdt_suspend_noirq()
363 imx7ulp_wdt_stop(&imx7ulp_wdt->wdd); in imx7ulp_wdt_suspend_noirq()
365 clk_disable_unprepare(imx7ulp_wdt->clk); in imx7ulp_wdt_suspend_noirq()
373 u32 timeout = imx7ulp_wdt->wdd.timeout * imx7ulp_wdt->hw->wdog_clock_rate; in imx7ulp_wdt_resume_noirq() local
376 ret = clk_prepare_enable(imx7ulp_wdt->clk); in imx7ulp_wdt_resume_noirq()
380 if (watchdog_active(&imx7ulp_wdt->wdd)) { in imx7ulp_wdt_resume_noirq()
381 imx7ulp_wdt_init(imx7ulp_wdt, timeout); in imx7ulp_wdt_resume_noirq()
382 imx7ulp_wdt_start(&imx7ulp_wdt->wdd); in imx7ulp_wdt_resume_noirq()
383 imx7ulp_wdt_ping(&imx7ulp_wdt->wdd); in imx7ulp_wdt_resume_noirq()
411 { .compatible = "fsl,imx7ulp-wdt", .data = &imx7ulp_wdt_hw, },
412 { .compatible = "fsl,imx8ulp-wdt", .data = &imx8ulp_wdt_hw, },
413 { .compatible = "fsl,imx93-wdt", .data = &imx93_wdt_hw, },
421 .name = "imx7ulp-wdt",