1 // SPDX-License-Identifier: GPL-2.0-only
11  * -----
12  * The timeout value is rounded to the next power of two clock cycles.
16  *     timeout = 2^(delay + 1) clock cycles
18  * Where 'delay' is the value written in PDC_WDT_CONFIG register.
21  * as a power of two number of watchdog clock cycles. The current implementation
25  * The following table shows how the user-configured timeout relates
29  * -----------------------------------
40 #include <linux/clk.h>
84 	struct clk *wdt_clk;
85 	struct clk *sys_clk;
93 	writel(PDC_WDT_TICKLE1_MAGIC, wdt->base + PDC_WDT_TICKLE1);  in pdc_wdt_keepalive()
94 	writel(PDC_WDT_TICKLE2_MAGIC, wdt->base + PDC_WDT_TICKLE2);  in pdc_wdt_keepalive()
104 	val = readl(wdt->base + PDC_WDT_CONFIG);  in pdc_wdt_stop()
106 	writel(val, wdt->base + PDC_WDT_CONFIG);  in pdc_wdt_stop()
116 	unsigned long clk_rate = clk_get_rate(wdt->wdt_clk);  in __pdc_wdt_set_timeout()
119 	val = readl(wdt->base + PDC_WDT_CONFIG) & ~PDC_WDT_CONFIG_DELAY_MASK;  in __pdc_wdt_set_timeout()
120 	val |= order_base_2(wdt->wdt_dev.timeout * clk_rate) - 1;  in __pdc_wdt_set_timeout()
121 	writel(val, wdt->base + PDC_WDT_CONFIG);  in __pdc_wdt_set_timeout()
129 	wdt->wdt_dev.timeout = new_timeout;  in pdc_wdt_set_timeout()
136 /* Start the watchdog timer (delay should already be set) */
144 	val = readl(wdt->base + PDC_WDT_CONFIG);  in pdc_wdt_start()
146 	writel(val, wdt->base + PDC_WDT_CONFIG);  in pdc_wdt_start()
157 	writel(0x1, wdt->base + PDC_WDT_SOFT_RESET);  in pdc_wdt_restart()
180 	struct device *dev = &pdev->dev;  in pdc_wdt_probe()
188 		return -ENOMEM;  in pdc_wdt_probe()
190 	pdc_wdt->base = devm_platform_ioremap_resource(pdev, 0);  in pdc_wdt_probe()
191 	if (IS_ERR(pdc_wdt->base))  in pdc_wdt_probe()
192 		return PTR_ERR(pdc_wdt->base);  in pdc_wdt_probe()
194 	pdc_wdt->sys_clk = devm_clk_get_enabled(dev, "sys");  in pdc_wdt_probe()
195 	if (IS_ERR(pdc_wdt->sys_clk)) {  in pdc_wdt_probe()
197 		return PTR_ERR(pdc_wdt->sys_clk);  in pdc_wdt_probe()
200 	pdc_wdt->wdt_clk = devm_clk_get_enabled(dev, "wdt");  in pdc_wdt_probe()
201 	if (IS_ERR(pdc_wdt->wdt_clk)) {  in pdc_wdt_probe()
203 		return PTR_ERR(pdc_wdt->wdt_clk);  in pdc_wdt_probe()
207 	clk_rate = clk_get_rate(pdc_wdt->wdt_clk);  in pdc_wdt_probe()
210 		return -EINVAL;  in pdc_wdt_probe()
215 		return -EINVAL;  in pdc_wdt_probe()
219 		pdc_wdt->wdt_dev.min_timeout = PDC_WDT_MIN_TIMEOUT + 1;  in pdc_wdt_probe()
221 		pdc_wdt->wdt_dev.min_timeout = PDC_WDT_MIN_TIMEOUT;  in pdc_wdt_probe()
223 	pdc_wdt->wdt_dev.info = &pdc_wdt_info;  in pdc_wdt_probe()
224 	pdc_wdt->wdt_dev.ops = &pdc_wdt_ops;  in pdc_wdt_probe()
228 	pdc_wdt->wdt_dev.max_timeout = div;  in pdc_wdt_probe()
229 	pdc_wdt->wdt_dev.timeout = PDC_WDT_DEF_TIMEOUT;  in pdc_wdt_probe()
230 	pdc_wdt->wdt_dev.parent = dev;  in pdc_wdt_probe()
231 	watchdog_set_drvdata(&pdc_wdt->wdt_dev, pdc_wdt);  in pdc_wdt_probe()
233 	watchdog_init_timeout(&pdc_wdt->wdt_dev, heartbeat, dev);  in pdc_wdt_probe()
235 	pdc_wdt_stop(&pdc_wdt->wdt_dev);  in pdc_wdt_probe()
238 	val = readl(pdc_wdt->base + PDC_WDT_TICKLE1);  in pdc_wdt_probe()
243 		pdc_wdt->wdt_dev.bootstatus |= WDIOF_CARDRESET;  in pdc_wdt_probe()
263 	watchdog_set_nowayout(&pdc_wdt->wdt_dev, nowayout);  in pdc_wdt_probe()
264 	watchdog_set_restart_priority(&pdc_wdt->wdt_dev, 128);  in pdc_wdt_probe()
268 	watchdog_stop_on_reboot(&pdc_wdt->wdt_dev);  in pdc_wdt_probe()
269 	watchdog_stop_on_unregister(&pdc_wdt->wdt_dev);  in pdc_wdt_probe()
270 	return devm_watchdog_register_device(dev, &pdc_wdt->wdt_dev);  in pdc_wdt_probe()
274 	{ .compatible = "img,pdc-wdt" },
281 		.name = "imgpdc-wdt",