Lines Matching refs:sioaddr

137 	unsigned short	sioaddr;  member
264 err = superio_enter(wd->sioaddr); in fintek_wdt_keepalive()
267 superio_select(wd->sioaddr, SIO_F71808FG_LD_WDT); in fintek_wdt_keepalive()
271 superio_set_bit(wd->sioaddr, F71808FG_REG_WDT_CONF, in fintek_wdt_keepalive()
275 superio_clear_bit(wd->sioaddr, F71808FG_REG_WDT_CONF, in fintek_wdt_keepalive()
279 superio_outb(wd->sioaddr, F71808FG_REG_WD_TIME, in fintek_wdt_keepalive()
282 superio_exit(wd->sioaddr); in fintek_wdt_keepalive()
298 err = superio_enter(wd->sioaddr); in fintek_wdt_start()
301 superio_select(wd->sioaddr, SIO_F71808FG_LD_WDT); in fintek_wdt_start()
307 superio_clear_bit(wd->sioaddr, SIO_REG_MFUNCT2, 3); in fintek_wdt_start()
308 superio_clear_bit(wd->sioaddr, SIO_REG_MFUNCT3, 3); in fintek_wdt_start()
314 superio_clear_bit(wd->sioaddr, SIO_REG_ROM_ADDR_SEL, 6); in fintek_wdt_start()
315 superio_set_bit(wd->sioaddr, SIO_REG_MFUNCT3, 4); in fintek_wdt_start()
317 superio_set_bit(wd->sioaddr, SIO_REG_MFUNCT1, 1); in fintek_wdt_start()
324 superio_clear_bit(wd->sioaddr, SIO_REG_MFUNCT1, 4); in fintek_wdt_start()
329 superio_set_bit(wd->sioaddr, SIO_REG_MFUNCT1, 1); in fintek_wdt_start()
334 superio_outb(wd->sioaddr, SIO_REG_MFUNCT3, in fintek_wdt_start()
335 superio_inb(wd->sioaddr, SIO_REG_MFUNCT3) & 0xcf); in fintek_wdt_start()
340 superio_clear_bit(wd->sioaddr, SIO_REG_CLOCK_SEL, 3); in fintek_wdt_start()
342 superio_outb(wd->sioaddr, SIO_REG_TSI_LEVEL_SEL, 0x5f & in fintek_wdt_start()
343 superio_inb(wd->sioaddr, SIO_REG_TSI_LEVEL_SEL)); in fintek_wdt_start()
348 superio_clear_bit(wd->sioaddr, SIO_REG_MFUNCT3, 5); in fintek_wdt_start()
359 tmp = superio_inb(wd->sioaddr, SIO_F81866_REG_PORT_SEL); in fintek_wdt_start()
362 superio_outb(wd->sioaddr, SIO_F81866_REG_PORT_SEL, tmp); in fintek_wdt_start()
364 superio_clear_bit(wd->sioaddr, SIO_F81866_REG_GPIO1, 5); in fintek_wdt_start()
376 superio_select(wd->sioaddr, SIO_F71808FG_LD_WDT); in fintek_wdt_start()
377 superio_set_bit(wd->sioaddr, SIO_REG_ENABLE, 0); in fintek_wdt_start()
380 superio_set_bit(wd->sioaddr, F81865_REG_WDO_CONF, in fintek_wdt_start()
383 superio_set_bit(wd->sioaddr, F71808FG_REG_WDO_CONF, in fintek_wdt_start()
386 superio_set_bit(wd->sioaddr, F71808FG_REG_WDT_CONF, in fintek_wdt_start()
391 u8 wdt_conf = superio_inb(wd->sioaddr, in fintek_wdt_start()
399 superio_outb(wd->sioaddr, F71808FG_REG_WDT_CONF, in fintek_wdt_start()
403 superio_clear_bit(wd->sioaddr, F71808FG_REG_WDT_CONF, in fintek_wdt_start()
408 superio_exit(wd->sioaddr); in fintek_wdt_start()
418 err = superio_enter(wd->sioaddr); in fintek_wdt_stop()
421 superio_select(wd->sioaddr, SIO_F71808FG_LD_WDT); in fintek_wdt_stop()
423 superio_clear_bit(wd->sioaddr, F71808FG_REG_WDT_CONF, in fintek_wdt_stop()
426 superio_exit(wd->sioaddr); in fintek_wdt_stop()
433 return (superio_inb(wd->sioaddr, SIO_REG_ENABLE) & BIT(0)) in fintek_wdt_is_running()
453 int sioaddr; in fintek_wdt_probe() local
459 sioaddr = res->start; in fintek_wdt_probe()
468 wd->sioaddr = sioaddr; in fintek_wdt_probe()
478 err = superio_enter(sioaddr); in fintek_wdt_probe()
481 superio_select(wd->sioaddr, SIO_F71808FG_LD_WDT); in fintek_wdt_probe()
483 wdt_conf = superio_inb(sioaddr, F71808FG_REG_WDT_CONF); in fintek_wdt_probe()
489 superio_outb(sioaddr, F71808FG_REG_WDT_CONF, in fintek_wdt_probe()
497 superio_exit(sioaddr); in fintek_wdt_probe()
537 static int __init fintek_wdt_find(int sioaddr) in fintek_wdt_find() argument
541 int err = superio_enter(sioaddr); in fintek_wdt_find()
545 devid = superio_inw(sioaddr, SIO_REG_MANID); in fintek_wdt_find()
552 devid = force_id ? force_id : superio_inw(sioaddr, SIO_REG_DEVID); in fintek_wdt_find()
598 (int)superio_inb(sioaddr, SIO_REG_DEVREV)); in fintek_wdt_find()
601 superio_exit(sioaddr); in fintek_wdt_find()