drivers/watchdog/f71808e_wdt.c

1 // SPDX-License-Identifier: GPL-2.0-or-later
4  *   Copyright (C) 2007-2009 Hans de Goede <hdegoede@redhat.com>           *
22 #define SIO_UNLOCK_KEY		0x87	/* Key to enable Super-I/O */
23 #define SIO_LOCK_KEY		0xAA	/* Key to disable Super-I/O */
31 #define SIO_F81866_REG_PORT_SEL	0x27	/* F81866 Multi-Function Register */
33 #define SIO_REG_MFUNCT1		0x29	/* Multi function select 1 */
34 #define SIO_REG_MFUNCT2		0x2a	/* Multi function select 2 */
35 #define SIO_REG_MFUNCT3		0x2b	/* Multi function select 3 */
74 					   pin number 63 */
96 	"Watchdog f71862fg reset output pin configuration. Choose pin 56 or 63"
125 /* Super-I/O Function prototypes */
144 	char		pulse_mode;	/* enable pulse output mode? */
191 		return -EBUSY;  in superio_enter()
218 		wd->timer_val = DIV_ROUND_UP(timeout, 60);  in fintek_wdt_set_timeout()
219 		wd->minutes_mode = true;  in fintek_wdt_set_timeout()
220 		timeout = wd->timer_val * 60;  in fintek_wdt_set_timeout()
222 		wd->timer_val = timeout;  in fintek_wdt_set_timeout()
223 		wd->minutes_mode = false;  in fintek_wdt_set_timeout()
226 	wdd->timeout = timeout;  in fintek_wdt_set_timeout()
235 	if (wd->type == f71868) {  in fintek_wdt_set_pulse_width()
242 		wd->pulse_val = 0;  in fintek_wdt_set_pulse_width()
244 		wd->pulse_val = 1;  in fintek_wdt_set_pulse_width()
246 		wd->pulse_val = 2;  in fintek_wdt_set_pulse_width()
248 		wd->pulse_val = 3;  in fintek_wdt_set_pulse_width()
251 		return -EINVAL;  in fintek_wdt_set_pulse_width()
254 	wd->pulse_mode = pw;  in fintek_wdt_set_pulse_width()
264 	err = superio_enter(wd->sioaddr);  in fintek_wdt_keepalive()
267 	superio_select(wd->sioaddr, SIO_F71808FG_LD_WDT);  in fintek_wdt_keepalive()
269 	if (wd->minutes_mode)  in fintek_wdt_keepalive()
271 		superio_set_bit(wd->sioaddr, F71808FG_REG_WDT_CONF,  in fintek_wdt_keepalive()
275 		superio_clear_bit(wd->sioaddr, F71808FG_REG_WDT_CONF,  in fintek_wdt_keepalive()
279 	superio_outb(wd->sioaddr, F71808FG_REG_WD_TIME,  in fintek_wdt_keepalive()
280 			   wd->timer_val);  in fintek_wdt_keepalive()
282 	superio_exit(wd->sioaddr);  in fintek_wdt_keepalive()
298 	err = superio_enter(wd->sioaddr);  in fintek_wdt_start()
301 	superio_select(wd->sioaddr, SIO_F71808FG_LD_WDT);  in fintek_wdt_start()
303 	/* Watchdog pin configuration */  in fintek_wdt_start()
304 	switch (wd->type) {  in fintek_wdt_start()
306 		/* Set pin 21 to GPIO23/WDTRST#, then to WDTRST# */  in fintek_wdt_start()
307 		superio_clear_bit(wd->sioaddr, SIO_REG_MFUNCT2, 3);  in fintek_wdt_start()
308 		superio_clear_bit(wd->sioaddr, SIO_REG_MFUNCT3, 3);  in fintek_wdt_start()
313 			/* SPI must be disabled first to use this pin! */  in fintek_wdt_start()
314 			superio_clear_bit(wd->sioaddr, SIO_REG_ROM_ADDR_SEL, 6);  in fintek_wdt_start()
315 			superio_set_bit(wd->sioaddr, SIO_REG_MFUNCT3, 4);  in fintek_wdt_start()
317 			superio_set_bit(wd->sioaddr, SIO_REG_MFUNCT1, 1);  in fintek_wdt_start()
323 		/* GPIO14 --> WDTRST# */  in fintek_wdt_start()
324 		superio_clear_bit(wd->sioaddr, SIO_REG_MFUNCT1, 4);  in fintek_wdt_start()
328 		/* Set pin 56 to WDTRST# */  in fintek_wdt_start()
329 		superio_set_bit(wd->sioaddr, SIO_REG_MFUNCT1, 1);  in fintek_wdt_start()
333 		/* set pin 40 to WDTRST# */  in fintek_wdt_start()
334 		superio_outb(wd->sioaddr, SIO_REG_MFUNCT3,  in fintek_wdt_start()
335 			superio_inb(wd->sioaddr, SIO_REG_MFUNCT3) & 0xcf);  in fintek_wdt_start()
340 		superio_clear_bit(wd->sioaddr, SIO_REG_CLOCK_SEL, 3);  in fintek_wdt_start()
341 		/* Set pin 27 to WDTRST# */  in fintek_wdt_start()
342 		superio_outb(wd->sioaddr, SIO_REG_TSI_LEVEL_SEL, 0x5f &  in fintek_wdt_start()
343 			superio_inb(wd->sioaddr, SIO_REG_TSI_LEVEL_SEL));  in fintek_wdt_start()
347 		/* Set pin 70 to WDTRST# */  in fintek_wdt_start()
348 		superio_clear_bit(wd->sioaddr, SIO_REG_MFUNCT3, 5);  in fintek_wdt_start()
355 		 * The PIN 70(GPIO15/WDTRST) is controlled by 2Ch:  in fintek_wdt_start()
356 		 *     BIT5: 0 -> WDTRST#  in fintek_wdt_start()
357 		 *           1 -> GPIO15  in fintek_wdt_start()
359 		tmp = superio_inb(wd->sioaddr, SIO_F81866_REG_PORT_SEL);  in fintek_wdt_start()
362 		superio_outb(wd->sioaddr, SIO_F81866_REG_PORT_SEL, tmp);  in fintek_wdt_start()
364 		superio_clear_bit(wd->sioaddr, SIO_F81866_REG_GPIO1, 5);  in fintek_wdt_start()
372 		err = -ENODEV;  in fintek_wdt_start()
376 	superio_select(wd->sioaddr, SIO_F71808FG_LD_WDT);  in fintek_wdt_start()
377 	superio_set_bit(wd->sioaddr, SIO_REG_ENABLE, 0);  in fintek_wdt_start()
379 	if (wd->type == f81865 || wd->type == f81866 || wd->type == f81966)  in fintek_wdt_start()
380 		superio_set_bit(wd->sioaddr, F81865_REG_WDO_CONF,  in fintek_wdt_start()
383 		superio_set_bit(wd->sioaddr, F71808FG_REG_WDO_CONF,  in fintek_wdt_start()
386 	superio_set_bit(wd->sioaddr, F71808FG_REG_WDT_CONF,  in fintek_wdt_start()
389 	if (wd->pulse_mode) {  in fintek_wdt_start()
390 		/* Select "pulse" output mode with given duration */  in fintek_wdt_start()
391 		u8 wdt_conf = superio_inb(wd->sioaddr,  in fintek_wdt_start()
395 		wdt_conf = (wdt_conf & 0xfc) | (wd->pulse_val & 0x03);  in fintek_wdt_start()
396 		/* Set WD_PULSE to "pulse" mode */  in fintek_wdt_start()
399 		superio_outb(wd->sioaddr, F71808FG_REG_WDT_CONF,  in fintek_wdt_start()
402 		/* Select "level" output mode */  in fintek_wdt_start()
403 		superio_clear_bit(wd->sioaddr, F71808FG_REG_WDT_CONF,  in fintek_wdt_start()
408 	superio_exit(wd->sioaddr);  in fintek_wdt_start()
418 	err = superio_enter(wd->sioaddr);  in fintek_wdt_stop()
421 	superio_select(wd->sioaddr, SIO_F71808FG_LD_WDT);  in fintek_wdt_stop()
423 	superio_clear_bit(wd->sioaddr, F71808FG_REG_WDT_CONF,  in fintek_wdt_stop()
426 	superio_exit(wd->sioaddr);  in fintek_wdt_stop()
433 	return (superio_inb(wd->sioaddr, SIO_REG_ENABLE) & BIT(0))  in fintek_wdt_is_running()
447 	struct device *dev = &pdev->dev;  in fintek_wdt_probe()
457 		return -ENXIO;  in fintek_wdt_probe()
459 	sioaddr = res->start;  in fintek_wdt_probe()
463 		return -ENOMEM;  in fintek_wdt_probe()
465 	pdata = dev->platform_data;  in fintek_wdt_probe()
467 	wd->type = pdata->type;  in fintek_wdt_probe()
468 	wd->sioaddr = sioaddr;  in fintek_wdt_probe()
469 	wd->ident.options = WDIOF_SETTIMEOUT  in fintek_wdt_probe()
474 	snprintf(wd->ident.identity,  in fintek_wdt_probe()
475 		sizeof(wd->ident.identity), "%s watchdog",  in fintek_wdt_probe()
476 		fintek_wdt_names[wd->type]);  in fintek_wdt_probe()
481 	superio_select(wd->sioaddr, SIO_F71808FG_LD_WDT);  in fintek_wdt_probe()
492 	wdd = &wd->wdd;  in fintek_wdt_probe()
495 		set_bit(WDOG_HW_RUNNING, &wdd->status);  in fintek_wdt_probe()
499 	wdd->parent		= dev;  in fintek_wdt_probe()
500 	wdd->info               = &wd->ident;  in fintek_wdt_probe()
501 	wdd->ops                = &fintek_wdt_ops;  in fintek_wdt_probe()
502 	wdd->min_timeout        = 1;  in fintek_wdt_probe()
503 	wdd->max_timeout        = WATCHDOG_MAX_TIMEOUT;  in fintek_wdt_probe()
512 		wdd->bootstatus = WDIOF_CARDRESET;  in fintek_wdt_probe()
519 	fintek_wdt_set_timeout(wdd, wdd->timeout);  in fintek_wdt_probe()
529 		set_bit(WDOG_HW_RUNNING, &wdd->status);  in fintek_wdt_probe()
548 		err = -ENODEV;  in fintek_wdt_find()
575 		err = -ENODEV;  in fintek_wdt_find()
592 		err = -ENODEV;  in fintek_wdt_find()
624 		return -EINVAL;  in fintek_wdt_init()
646 	fintek_wdt_pdev = platform_device_register_resndata(NULL, DRVNAME, -1,  in fintek_wdt_init()