Lines Matching refs:base_addr
60 void __iomem *base_addr; member
81 iowrite32(IRQ, amd_axi_w1_local->base_addr + AXIW1_IRQE_REG); in amd_axi_w1_wait_irq_interruptible_timeout()
114 while ((ioread32(amd_axi_w1_local->base_addr + AXIW1_STAT_REG) & AXIW1_READY) == 0) { in amd_axi_w1_touch_bit()
123 iowrite32(AXIW1_READBIT, amd_axi_w1_local->base_addr + AXIW1_INST_REG); in amd_axi_w1_touch_bit()
127 amd_axi_w1_local->base_addr + AXIW1_INST_REG); in amd_axi_w1_touch_bit()
130 iowrite32(AXIW1_GO, amd_axi_w1_local->base_addr + AXIW1_CTRL_REG); in amd_axi_w1_touch_bit()
133 while ((ioread32(amd_axi_w1_local->base_addr + AXIW1_STAT_REG) & AXIW1_DONE) != 1) { in amd_axi_w1_touch_bit()
141 val = (u8)(ioread32(amd_axi_w1_local->base_addr + AXIW1_DATA_REG) & AXIW1_READDATA); in amd_axi_w1_touch_bit()
144 iowrite32(AXI_CLEAR, amd_axi_w1_local->base_addr + AXIW1_CTRL_REG); in amd_axi_w1_touch_bit()
162 while ((ioread32(amd_axi_w1_local->base_addr + AXIW1_STAT_REG) & AXIW1_READY) == 0) { in amd_axi_w1_read_byte()
170 iowrite32(AXIW1_READBYTE, amd_axi_w1_local->base_addr + AXIW1_INST_REG); in amd_axi_w1_read_byte()
173 iowrite32(AXIW1_GO, amd_axi_w1_local->base_addr + AXIW1_CTRL_REG); in amd_axi_w1_read_byte()
176 while ((ioread32(amd_axi_w1_local->base_addr + AXIW1_STAT_REG) & AXIW1_DONE) != 1) { in amd_axi_w1_read_byte()
183 val = (u8)(ioread32(amd_axi_w1_local->base_addr + AXIW1_DATA_REG) & 0x000000FF); in amd_axi_w1_read_byte()
186 iowrite32(AXI_CLEAR, amd_axi_w1_local->base_addr + AXIW1_CTRL_REG); in amd_axi_w1_read_byte()
203 while ((ioread32(amd_axi_w1_local->base_addr + AXIW1_STAT_REG) & AXIW1_READY) == 0) { in amd_axi_w1_write_byte()
211 iowrite32(AXIW1_WRITEBYTE + val, amd_axi_w1_local->base_addr + AXIW1_INST_REG); in amd_axi_w1_write_byte()
214 iowrite32(AXIW1_GO, amd_axi_w1_local->base_addr + AXIW1_CTRL_REG); in amd_axi_w1_write_byte()
217 while ((ioread32(amd_axi_w1_local->base_addr + AXIW1_STAT_REG) & AXIW1_DONE) != 1) { in amd_axi_w1_write_byte()
225 iowrite32(AXI_CLEAR, amd_axi_w1_local->base_addr + AXIW1_CTRL_REG); in amd_axi_w1_write_byte()
241 iowrite32(AXI_RESET, amd_axi_w1_local->base_addr + AXIW1_CTRL_REG); in amd_axi_w1_reset_bus()
244 while ((ioread32(amd_axi_w1_local->base_addr + AXIW1_STAT_REG) & AXIW1_READY) == 0) { in amd_axi_w1_reset_bus()
251 iowrite32(AXIW1_INITPRES, amd_axi_w1_local->base_addr + AXIW1_INST_REG); in amd_axi_w1_reset_bus()
254 iowrite32(AXIW1_GO, amd_axi_w1_local->base_addr + AXIW1_CTRL_REG); in amd_axi_w1_reset_bus()
257 while ((ioread32(amd_axi_w1_local->base_addr + AXIW1_STAT_REG) & AXIW1_DONE) != 1) { in amd_axi_w1_reset_bus()
263 if ((ioread32(amd_axi_w1_local->base_addr + AXIW1_STAT_REG) & AXIW1_PRESENCE) != 0) in amd_axi_w1_reset_bus()
267 iowrite32(AXI_CLEAR, amd_axi_w1_local->base_addr + AXIW1_CTRL_REG); in amd_axi_w1_reset_bus()
275 iowrite32(AXI_RESET, amd_axi_w1_local->base_addr + AXIW1_CTRL_REG); in amd_axi_w1_reset()
276 iowrite32(AXI_CLEAR, amd_axi_w1_local->base_addr + AXIW1_INST_REG); in amd_axi_w1_reset()
277 iowrite32(AXI_CLEAR, amd_axi_w1_local->base_addr + AXIW1_IRQE_REG); in amd_axi_w1_reset()
278 iowrite32(AXI_CLEAR, amd_axi_w1_local->base_addr + AXIW1_STAT_REG); in amd_axi_w1_reset()
279 iowrite32(AXI_CLEAR, amd_axi_w1_local->base_addr + AXIW1_DATA_REG); in amd_axi_w1_reset()
287 iowrite32(AXI_CLEAR, amd_axi_w1_local->base_addr + AXIW1_IRQE_REG); in amd_axi_w1_irq()
308 lp->base_addr = devm_platform_ioremap_resource(pdev, 0); in amd_axi_w1_probe()
309 if (IS_ERR(lp->base_addr)) in amd_axi_w1_probe()
310 return PTR_ERR(lp->base_addr); in amd_axi_w1_probe()
328 if (ioread32(lp->base_addr + AXIW1_IPID_REG) != AXIW1_IPID) { in amd_axi_w1_probe()
343 val = ioread32(lp->base_addr + AXIW1_IPVER_REG); in amd_axi_w1_probe()