Lines Matching full:raw
20 struct via_display_timing raw; in via_set_primary_timing() local
22 raw.hor_total = timing->hor_total / 8 - 5; in via_set_primary_timing()
23 raw.hor_addr = timing->hor_addr / 8 - 1; in via_set_primary_timing()
24 raw.hor_blank_start = timing->hor_blank_start / 8 - 1; in via_set_primary_timing()
25 raw.hor_blank_end = timing->hor_blank_end / 8 - 1; in via_set_primary_timing()
26 raw.hor_sync_start = timing->hor_sync_start / 8; in via_set_primary_timing()
27 raw.hor_sync_end = timing->hor_sync_end / 8; in via_set_primary_timing()
28 raw.ver_total = timing->ver_total - 2; in via_set_primary_timing()
29 raw.ver_addr = timing->ver_addr - 1; in via_set_primary_timing()
30 raw.ver_blank_start = timing->ver_blank_start - 1; in via_set_primary_timing()
31 raw.ver_blank_end = timing->ver_blank_end - 1; in via_set_primary_timing()
32 raw.ver_sync_start = timing->ver_sync_start - 1; in via_set_primary_timing()
33 raw.ver_sync_end = timing->ver_sync_end - 1; in via_set_primary_timing()
38 via_write_reg(VIACR, 0x00, raw.hor_total & 0xFF); in via_set_primary_timing()
39 via_write_reg(VIACR, 0x01, raw.hor_addr & 0xFF); in via_set_primary_timing()
40 via_write_reg(VIACR, 0x02, raw.hor_blank_start & 0xFF); in via_set_primary_timing()
41 via_write_reg_mask(VIACR, 0x03, raw.hor_blank_end & 0x1F, 0x1F); in via_set_primary_timing()
42 via_write_reg(VIACR, 0x04, raw.hor_sync_start & 0xFF); in via_set_primary_timing()
43 via_write_reg_mask(VIACR, 0x05, (raw.hor_sync_end & 0x1F) in via_set_primary_timing()
44 | (raw.hor_blank_end << (7 - 5) & 0x80), 0x9F); in via_set_primary_timing()
45 via_write_reg(VIACR, 0x06, raw.ver_total & 0xFF); in via_set_primary_timing()
46 via_write_reg_mask(VIACR, 0x07, (raw.ver_total >> 8 & 0x01) in via_set_primary_timing()
47 | (raw.ver_addr >> (8 - 1) & 0x02) in via_set_primary_timing()
48 | (raw.ver_sync_start >> (8 - 2) & 0x04) in via_set_primary_timing()
49 | (raw.ver_blank_start >> (8 - 3) & 0x08) in via_set_primary_timing()
50 | (raw.ver_total >> (9 - 5) & 0x20) in via_set_primary_timing()
51 | (raw.ver_addr >> (9 - 6) & 0x40) in via_set_primary_timing()
52 | (raw.ver_sync_start >> (9 - 7) & 0x80), 0xEF); in via_set_primary_timing()
53 via_write_reg_mask(VIACR, 0x09, raw.ver_blank_start >> (9 - 5) & 0x20, in via_set_primary_timing()
55 via_write_reg(VIACR, 0x10, raw.ver_sync_start & 0xFF); in via_set_primary_timing()
56 via_write_reg_mask(VIACR, 0x11, raw.ver_sync_end & 0x0F, 0x0F); in via_set_primary_timing()
57 via_write_reg(VIACR, 0x12, raw.ver_addr & 0xFF); in via_set_primary_timing()
58 via_write_reg(VIACR, 0x15, raw.ver_blank_start & 0xFF); in via_set_primary_timing()
59 via_write_reg(VIACR, 0x16, raw.ver_blank_end & 0xFF); in via_set_primary_timing()
60 via_write_reg_mask(VIACR, 0x33, (raw.hor_sync_start >> (8 - 4) & 0x10) in via_set_primary_timing()
61 | (raw.hor_blank_end >> (6 - 5) & 0x20), 0x30); in via_set_primary_timing()
62 via_write_reg_mask(VIACR, 0x35, (raw.ver_total >> 10 & 0x01) in via_set_primary_timing()
63 | (raw.ver_sync_start >> (10 - 1) & 0x02) in via_set_primary_timing()
64 | (raw.ver_addr >> (10 - 2) & 0x04) in via_set_primary_timing()
65 | (raw.ver_blank_start >> (10 - 3) & 0x08), 0x0F); in via_set_primary_timing()
66 via_write_reg_mask(VIACR, 0x36, raw.hor_total >> (8 - 3) & 0x08, 0x08); in via_set_primary_timing()
78 struct via_display_timing raw; in via_set_secondary_timing() local
80 raw.hor_total = timing->hor_total - 1; in via_set_secondary_timing()
81 raw.hor_addr = timing->hor_addr - 1; in via_set_secondary_timing()
82 raw.hor_blank_start = timing->hor_blank_start - 1; in via_set_secondary_timing()
83 raw.hor_blank_end = timing->hor_blank_end - 1; in via_set_secondary_timing()
84 raw.hor_sync_start = timing->hor_sync_start - 1; in via_set_secondary_timing()
85 raw.hor_sync_end = timing->hor_sync_end - 1; in via_set_secondary_timing()
86 raw.ver_total = timing->ver_total - 1; in via_set_secondary_timing()
87 raw.ver_addr = timing->ver_addr - 1; in via_set_secondary_timing()
88 raw.ver_blank_start = timing->ver_blank_start - 1; in via_set_secondary_timing()
89 raw.ver_blank_end = timing->ver_blank_end - 1; in via_set_secondary_timing()
90 raw.ver_sync_start = timing->ver_sync_start - 1; in via_set_secondary_timing()
91 raw.ver_sync_end = timing->ver_sync_end - 1; in via_set_secondary_timing()
93 via_write_reg(VIACR, 0x50, raw.hor_total & 0xFF); in via_set_secondary_timing()
94 via_write_reg(VIACR, 0x51, raw.hor_addr & 0xFF); in via_set_secondary_timing()
95 via_write_reg(VIACR, 0x52, raw.hor_blank_start & 0xFF); in via_set_secondary_timing()
96 via_write_reg(VIACR, 0x53, raw.hor_blank_end & 0xFF); in via_set_secondary_timing()
97 via_write_reg(VIACR, 0x54, (raw.hor_blank_start >> 8 & 0x07) in via_set_secondary_timing()
98 | (raw.hor_blank_end >> (8 - 3) & 0x38) in via_set_secondary_timing()
99 | (raw.hor_sync_start >> (8 - 6) & 0xC0)); in via_set_secondary_timing()
100 via_write_reg_mask(VIACR, 0x55, (raw.hor_total >> 8 & 0x0F) in via_set_secondary_timing()
101 | (raw.hor_addr >> (8 - 4) & 0x70), 0x7F); in via_set_secondary_timing()
102 via_write_reg(VIACR, 0x56, raw.hor_sync_start & 0xFF); in via_set_secondary_timing()
103 via_write_reg(VIACR, 0x57, raw.hor_sync_end & 0xFF); in via_set_secondary_timing()
104 via_write_reg(VIACR, 0x58, raw.ver_total & 0xFF); in via_set_secondary_timing()
105 via_write_reg(VIACR, 0x59, raw.ver_addr & 0xFF); in via_set_secondary_timing()
106 via_write_reg(VIACR, 0x5A, raw.ver_blank_start & 0xFF); in via_set_secondary_timing()
107 via_write_reg(VIACR, 0x5B, raw.ver_blank_end & 0xFF); in via_set_secondary_timing()
108 via_write_reg(VIACR, 0x5C, (raw.ver_blank_start >> 8 & 0x07) in via_set_secondary_timing()
109 | (raw.ver_blank_end >> (8 - 3) & 0x38) in via_set_secondary_timing()
110 | (raw.hor_sync_end >> (8 - 6) & 0x40) in via_set_secondary_timing()
111 | (raw.hor_sync_start >> (10 - 7) & 0x80)); in via_set_secondary_timing()
112 via_write_reg(VIACR, 0x5D, (raw.ver_total >> 8 & 0x07) in via_set_secondary_timing()
113 | (raw.ver_addr >> (8 - 3) & 0x38) in via_set_secondary_timing()
114 | (raw.hor_blank_end >> (11 - 6) & 0x40) in via_set_secondary_timing()
115 | (raw.hor_sync_start >> (11 - 7) & 0x80)); in via_set_secondary_timing()
116 via_write_reg(VIACR, 0x5E, raw.ver_sync_start & 0xFF); in via_set_secondary_timing()
117 via_write_reg(VIACR, 0x5F, (raw.ver_sync_end & 0x1F) in via_set_secondary_timing()
118 | (raw.ver_sync_start >> (8 - 5) & 0xE0)); in via_set_secondary_timing()