466 	viafb_write_reg_mask(CR11, VIACR, BIT7, BIT7);  in viafb_lock_crt()
471 	viafb_write_reg_mask(CR11, VIACR, 0, BIT7);  in viafb_unlock_crt()
472 	viafb_write_reg_mask(CR47, VIACR, 0, BIT0);  in viafb_unlock_crt()
668 	viafb_write_reg_mask(0x1A, VIASR, 0x00, 0x01);  in viafb_set_primary_color_register()
674 	viafb_write_reg_mask(0x1A, VIASR, 0x01, 0x01);  in viafb_set_secondary_color_register()
945 	viafb_write_reg_mask(CR03, VIACR, 0x80, BIT7);  in load_fix_bit_crtc_reg()
947 	viafb_write_reg_mask(CR35, VIACR, 0x10, BIT4);  in load_fix_bit_crtc_reg()
949 	viafb_write_reg_mask(CR33, VIACR, 0x06, BIT0 + BIT1 + BIT2);  in load_fix_bit_crtc_reg()
957 		viafb_write_reg_mask(CR33, VIACR, 0x08, BIT3);  in load_fix_bit_crtc_reg()
960 		viafb_write_reg_mask(SR1A, VIASR, 0x02, BIT1);  in load_fix_bit_crtc_reg()
993 			viafb_write_reg_mask(cr_index, VIACR, data, reg_mask);  in viafb_load_reg()
995 			viafb_write_reg_mask(cr_index, VIASR, data, reg_mask);  in viafb_load_reg()
1667 		viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0);  in viafb_init_dac()
1669 		viafb_write_reg_mask(SR1B, VIASR, 0x00, BIT7 + BIT6);  in viafb_init_dac()
1676 		viafb_write_reg_mask(SR1B, VIASR, 0xC0, BIT7 + BIT6);  in viafb_init_dac()
1680 		viafb_write_reg_mask(CR6A, VIACR, 0x40, BIT6);  in viafb_init_dac()
1681 		viafb_write_reg_mask(SR1A, VIASR, 0x01, BIT0);  in viafb_init_dac()
1688 		viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0);  in viafb_init_dac()
1696 	viafb_write_reg_mask(SR01, VIASR, 0x20, BIT5);  in device_screen_off()
1702 	viafb_write_reg_mask(SR01, VIASR, 0x00, BIT5);  in device_screen_on()
1713 		viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5);  in set_display_channel()
1717 		viafb_write_reg_mask(CRD2, VIACR, 0x10, BIT4 + BIT5);  in set_display_channel()
1720 		viafb_write_reg_mask(CRD2, VIACR, 0x30, BIT4 + BIT5);  in set_display_channel()
1725 			viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5);  in set_display_channel()
1728 			viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT4 + BIT5);  in set_display_channel()
1800 	viafb_write_reg_mask(0x15, VIASR, 0xA2, 0xA2);  in hw_init()
1844 			viafb_write_reg_mask(index, port, value, mask);  in viafb_setmode()
2033 	viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6);  in enable_second_display_channel()
2034 	viafb_write_reg_mask(CR6A, VIACR, BIT7, BIT7);  in enable_second_display_channel()
2035 	viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6);  in enable_second_display_channel()
2041 	viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6);  in disable_second_display_channel()
2042 	viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT7);  in disable_second_display_channel()
2043 	viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6);  in disable_second_display_channel()
2053 			viafb_write_reg_mask(CR96, VIACR,  in viafb_set_dpa_gfx()
2057 			viafb_write_reg_mask(SR1E, VIASR,  in viafb_set_dpa_gfx()
2059 			viafb_write_reg_mask(SR2A, VIASR,  in viafb_set_dpa_gfx()
2062 			viafb_write_reg_mask(SR1B, VIASR,  in viafb_set_dpa_gfx()
2064 			viafb_write_reg_mask(SR2A, VIASR,  in viafb_set_dpa_gfx()
2072 			viafb_write_reg_mask(CR9B, VIACR,  in viafb_set_dpa_gfx()
2076 			viafb_write_reg_mask(SR65, VIASR,  in viafb_set_dpa_gfx()
2083 			viafb_write_reg_mask(CR97, VIACR,  in viafb_set_dpa_gfx()
2090 			viafb_write_reg_mask(CR99, VIACR,  in viafb_set_dpa_gfx()
2097 			viafb_write_reg_mask(CR97, VIACR,  in viafb_set_dpa_gfx()
2099 			viafb_write_reg_mask(CR99, VIACR,  in viafb_set_dpa_gfx()