38 	unsigned char sr2a = 0, sr1e = 0, sr3e = 0;  in viafb_tmds_trasmitter_identify()
45 		viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1);  in viafb_tmds_trasmitter_identify()
52 		viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1);  in viafb_tmds_trasmitter_identify()
55 		viafb_write_reg_mask(SR1E, VIASR, 0xC0, BIT6 + BIT7);  in viafb_tmds_trasmitter_identify()
61 		viafb_write_reg_mask(SR1E, VIASR, 0xF0, BIT4 +  in viafb_tmds_trasmitter_identify()
64 	    0 = Emulate I2C and DDC bus by GPIO2/3/4. */  in viafb_tmds_trasmitter_identify()
66 		viafb_write_reg_mask(SR3E, VIASR, 0x0, BIT5);  in viafb_tmds_trasmitter_identify()
79 		tmds_register_write(0x08, 0x3b);  in viafb_tmds_trasmitter_identify()
90 			tmds_register_write(0x08, 0x3b);  in viafb_tmds_trasmitter_identify()
157 	return 0;  in tmds_register_read_bytes()
181 	u8 RegSR1E = 0, RegSR3E = 0, RegCR6B = 0, RegCR91 = 0,  in viafb_dvi_sense()
182 		RegCR93 = 0, RegCR9B = 0, data;  in viafb_dvi_sense()
190 		viafb_write_reg(SR1E, VIASR, RegSR1E | 0x30);  in viafb_dvi_sense()
192 		/* CR6B[0]VCK Input Selection: 1 = External clock. */  in viafb_dvi_sense()
194 		viafb_write_reg(CR6B, VIACR, RegCR6B | 0x08);  in viafb_dvi_sense()
197 		   [0] Software Control Power Sequence */  in viafb_dvi_sense()
199 		viafb_write_reg(CR91, VIACR, 0x1D);  in viafb_dvi_sense()
204 		   CR93[3:1] DI1 Clock Adjust. CR93[0] DI1 enable */  in viafb_dvi_sense()
206 		viafb_write_reg(CR93, VIACR, 0x01);  in viafb_dvi_sense()
210 		viafb_write_reg(SR1E, VIASR, RegSR1E | 0xF0);  in viafb_dvi_sense()
213 		   0 = Emulate I2C and DDC bus by GPIO2/3/4. */  in viafb_dvi_sense()
215 		viafb_write_reg(SR3E, VIASR, RegSR3E & (~0x20));  in viafb_dvi_sense()
218 		   [0] Software Control Power Sequence */  in viafb_dvi_sense()
220 		viafb_write_reg(CR91, VIACR, 0x1D);  in viafb_dvi_sense()
223 		display.CR9B[2:0] DVP1 Clock Adjust */  in viafb_dvi_sense()
225 		viafb_write_reg(CR9B, VIACR, 0x01);  in viafb_dvi_sense()
228 	data = (u8) tmds_register_read(0x09);  in viafb_dvi_sense()
229 	if (data & 0x04)  in viafb_dvi_sense()
260 	viaparinfo->chip_info->tmds_chip_info.tmds_chip_target_addr = 0xA0;  in viafb_dvi_query_EDID()
262 	data0 = (u8) tmds_register_read(0x00);  in viafb_dvi_query_EDID()
263 	data1 = (u8) tmds_register_read(0x01);  in viafb_dvi_query_EDID()
264 	if ((data0 == 0) && (data1 == 0xFF)) {  in viafb_dvi_query_EDID()
284 	tmds_chip->tmds_chip_target_addr = 0xA0;  in dvi_get_panel_size_from_DDCv1()
285 	for (i = 0x25; i < 0x6D; i++) {  in dvi_get_panel_size_from_DDCv1()
287 		case 0x36:  in dvi_get_panel_size_from_DDCv1()
288 		case 0x48:  in dvi_get_panel_size_from_DDCv1()
289 		case 0x5A:  in dvi_get_panel_size_from_DDCv1()
290 		case 0x6C:  in dvi_get_panel_size_from_DDCv1()
292 			if (!(EDID_DATA[0] || EDID_DATA[1])) {  in dvi_get_panel_size_from_DDCv1()
294 				if (EDID_DATA[3] == 0xFD) {  in dvi_get_panel_size_from_DDCv1()
319 		viafb_read_reg(VIACR, CRD2) | 0x08);  in viafb_dvi_disable()
325 	viafb_write_reg_mask(SR1B, VIASR, 0, BIT1);  in dvi_patch_skew_dvp0()
326 	viafb_write_reg_mask(SR2A, VIASR, 0, BIT4);  in dvi_patch_skew_dvp0()
334 				viafb_write_reg_mask(CR96, VIACR, 0x03,  in dvi_patch_skew_dvp0()
337 				viafb_write_reg_mask(CR96, VIACR, 0x07,  in dvi_patch_skew_dvp0()
344 			viafb_write_reg_mask(CR96, VIACR, 0x07,  in dvi_patch_skew_dvp0()
346 			viafb_write_reg_mask(SR1B, VIASR, 0x02, BIT1);  in dvi_patch_skew_dvp0()
347 			viafb_write_reg_mask(SR2A, VIASR, 0x10, BIT4);  in dvi_patch_skew_dvp0()
363 			viafb_write_reg_mask(CR99, VIACR, 0x03, BIT0 + BIT1);  in dvi_patch_skew_dvp_low()
369 			viafb_write_reg_mask(CR99, VIACR, 0x08,  in dvi_patch_skew_dvp_low()
376 			viafb_write_reg_mask(CR99, VIACR, 0x0F,  in dvi_patch_skew_dvp_low()
395 		viafb_write_reg_mask(CR6B, VIACR, 0x01, BIT0);  in viafb_dvi_enable()
396 		viafb_write_reg_mask(CR6C, VIACR, 0x21, BIT0 + BIT5);  in viafb_dvi_enable()
399 			tmds_register_write(0x88, 0x3b);  in viafb_dvi_enable()
403 			via_write_reg_mask(VIACR, 0x91, 0x00, 0x20);  in viafb_dvi_enable()
408 			viafb_write_reg_mask(CR93, VIACR, 0x21, BIT0 + BIT5);  in viafb_dvi_enable()
412 			tmds_register_write(0x88, 0x3b);  in viafb_dvi_enable()
416 			via_write_reg_mask(VIACR, 0x91, 0x00, 0x20);  in viafb_dvi_enable()
420 			viafb_write_reg_mask(CR91, VIACR, 0x1f, 0x1f);  in viafb_dvi_enable()
421 			viafb_write_reg_mask(CR88, VIACR, 0x00, BIT6 + BIT0);  in viafb_dvi_enable()
424 					data = 0x3F;  in viafb_dvi_enable()
426 					data = 0x37;  in viafb_dvi_enable()
431 					0x08, data);  in viafb_dvi_enable()
438 			via_write_reg_mask(VIACR, CR97, 0x03, 0x03);  in viafb_dvi_enable()
440 		via_write_reg_mask(VIACR, 0x91, 0x00, 0x20);  in viafb_dvi_enable()
448 		via_write_reg_mask(VIACR, 0x91, 0x00, 0x20);  in viafb_dvi_enable()
453 		viafb_write_reg_mask(CR91, VIACR, 0, BIT7);  in viafb_dvi_enable()
456 		viafb_write_reg_mask(CRD2, VIACR, 0, BIT3);  in viafb_dvi_enable()
462 		viafb_write_reg_mask(CR79, VIACR, 0x00, BIT0);  in viafb_dvi_enable()