Lines Matching refs:mclks
659 int nvclks, mclks, pclks, vpagemiss, crtpagemiss, vbs; in nv4CalcArbitration() local
682 mclks = 5; in nv4CalcArbitration()
683 mclks += 3; in nv4CalcArbitration()
684 mclks += 1; in nv4CalcArbitration()
685 mclks += cas; in nv4CalcArbitration()
686 mclks += 1; in nv4CalcArbitration()
687 mclks += 1; in nv4CalcArbitration()
688 mclks += 1; in nv4CalcArbitration()
689 mclks += 1; in nv4CalcArbitration()
696 mclks+=4; in nv4CalcArbitration()
705 mclk_loop = mclks+mclk_extra; in nv4CalcArbitration()
840 int nvclks, mclks, pclks, vpagemiss, crtpagemiss; in nv10CalcArbitration() local
870 mclks = 1; /* 2 edge sync. may be very close to edge so just put one. */ in nv10CalcArbitration()
872 mclks += 1; /* arb_hp_req */ in nv10CalcArbitration()
873 mclks += 5; /* ap_hp_req tiling pipeline */ in nv10CalcArbitration()
875 mclks += 2; /* tc_req latency fifo */ in nv10CalcArbitration()
876 mclks += 2; /* fb_cas_n_ memory request to fbio block */ in nv10CalcArbitration()
877 mclks += 7; /* sm_d_rdv data returned from fbio block */ in nv10CalcArbitration()
882 mclks += 4; in nv10CalcArbitration()
884 mclks += 2; in nv10CalcArbitration()
887 mclks += 2; in nv10CalcArbitration()
889 mclks += 1; in nv10CalcArbitration()
909 mclks+=4; /* Mp can get in with a burst of 8. */ in nv10CalcArbitration()
918 mclk_loop = mclks+mclk_extra; in nv10CalcArbitration()
920 us_m_min = mclks * 1000*1000 / mclk_freq; /* Minimum Mclk latency in us */ in nv10CalcArbitration()