Lines Matching +full:0 +full:x000000ff
6 /* Video Frame 0&1 start address registers */
7 #define LCD_SPU_DMA_START_ADDR_Y0 0x00C0
8 #define LCD_SPU_DMA_START_ADDR_U0 0x00C4
9 #define LCD_SPU_DMA_START_ADDR_V0 0x00C8
10 #define LCD_CFG_DMA_START_ADDR_0 0x00CC /* Cmd address */
11 #define LCD_SPU_DMA_START_ADDR_Y1 0x00D0
12 #define LCD_SPU_DMA_START_ADDR_U1 0x00D4
13 #define LCD_SPU_DMA_START_ADDR_V1 0x00D8
14 #define LCD_CFG_DMA_START_ADDR_1 0x00DC /* Cmd address */
17 #define LCD_SPU_DMA_PITCH_YC 0x00E0
20 #define LCD_SPU_DMA_PITCH_UV 0x00E4
25 #define LCD_SPUT_DMA_OVSA_HPXL_VLN 0x00E8
26 #define CFG_DMA_OVSA_VLN(y) ((y) << 16) /* 0~0xfff */
27 #define CFG_DMA_OVSA_HPXL(x) (x) /* 0~0xfff */
30 #define LCD_SPU_DMA_HPXL_VLN 0x00EC
35 #define LCD_SPU_DZM_HPXL_VLN 0x00F0
39 /* Graphic Frame 0&1 Starting Address Register */
40 #define LCD_CFG_GRA_START_ADDR0 0x00F4
41 #define LCD_CFG_GRA_START_ADDR1 0x00F8
44 #define LCD_CFG_GRA_PITCH 0x00FC
47 #define LCD_SPU_GRA_OVSA_HPXL_VLN 0x0100
52 #define LCD_SPU_GRA_HPXL_VLN 0x0104
57 #define LCD_SPU_GZM_HPXL_VLN 0x0108
62 #define LCD_SPU_HWC_OVSA_HPXL_VLN 0x010C
67 #define LCD_SPU_HWC_HPXL_VLN 0x0110
72 #define LCD_SPUT_V_H_TOTAL 0x0114
77 #define LCD_SPU_V_H_ACTIVE 0x0118
82 #define LCD_SPU_H_PORCH 0x011C
85 #define LCD_SPU_V_PORCH 0x0120
90 #define LCD_SPU_BLANKCOLOR 0x0124
91 #define CFG_BLANKCOLOR_MASK 0x00FFFFFF
92 #define CFG_BLANKCOLOR_R_MASK 0x000000FF
93 #define CFG_BLANKCOLOR_G_MASK 0x0000FF00
94 #define CFG_BLANKCOLOR_B_MASK 0x00FF0000
97 #define LCD_SPU_ALPHA_COLOR1 0x0128
98 #define CFG_HWC_COLOR1 0x00FFFFFF
102 #define CFG_HWC_COLOR1_R_MASK 0x000000FF
103 #define CFG_HWC_COLOR1_G_MASK 0x0000FF00
104 #define CFG_HWC_COLOR1_B_MASK 0x00FF0000
105 #define LCD_SPU_ALPHA_COLOR2 0x012C
106 #define CFG_HWC_COLOR2 0x00FFFFFF
107 #define CFG_HWC_COLOR2_R_MASK 0x000000FF
108 #define CFG_HWC_COLOR2_G_MASK 0x0000FF00
109 #define CFG_HWC_COLOR2_B_MASK 0x00FF0000
112 #define LCD_SPU_COLORKEY_Y 0x0130
114 #define CFG_CKEY_Y2_MASK 0xFF000000
116 #define CFG_CKEY_Y1_MASK 0x00FF0000
118 #define CFG_CKEY_Y_MASK 0x0000FF00
120 #define CFG_ALPHA_Y_MASK 0x000000FF
121 #define LCD_SPU_COLORKEY_U 0x0134
123 #define CFG_CKEY_U2_MASK 0xFF000000
125 #define CFG_CKEY_U1_MASK 0x00FF0000
127 #define CFG_CKEY_U_MASK 0x0000FF00
129 #define CFG_ALPHA_U_MASK 0x000000FF
130 #define LCD_SPU_COLORKEY_V 0x0138
132 #define CFG_CKEY_V2_MASK 0xFF000000
134 #define CFG_CKEY_V1_MASK 0x00FF0000
136 #define CFG_CKEY_V_MASK 0x0000FF00
138 #define CFG_ALPHA_V_MASK 0x000000FF
141 #define LCD_SPU_SPI_RXDATA 0x0140
144 #define LCD_SPU_ISA_RSDATA 0x0144
145 #define ISA_RXDATA_16BIT_1_DATA_MASK 0x000000FF
146 #define ISA_RXDATA_16BIT_2_DATA_MASK 0x0000FF00
147 #define ISA_RXDATA_16BIT_3_DATA_MASK 0x00FF0000
148 #define ISA_RXDATA_16BIT_4_DATA_MASK 0xFF000000
149 #define ISA_RXDATA_32BIT_1_DATA_MASK 0x00FFFFFF
152 #define LCD_SPU_HWC_RDDAT 0x0158
155 #define LCD_SPU_GAMMA_RDDAT 0x015c
156 #define CFG_GAMMA_RDDAT_MASK 0x000000FF
159 #define LCD_SPU_PALETTE_RDDAT 0x0160
160 #define CFG_PALETTE_RDDAT_MASK 0x00FFFFFF
163 #define LCD_SPU_IOPAD_IN 0x0178
164 #define CFG_IOPAD_IN_MASK 0x0FFFFFFF
167 #define LCD_CFG_RDREG5F 0x017C
168 #define IRE_FRAME_CNT_MASK 0x000000C0
169 #define IPE_FRAME_CNT_MASK 0x00000030
170 #define GRA_FRAME_CNT_MASK 0x0000000C /* Graphic */
171 #define DMA_FRAME_CNT_MASK 0x00000003 /* Video */
174 #define LCD_SPU_SPI_CTRL 0x0180
175 #define CFG_SCLKCNT(div) ((div) << 24) /* 0xFF~0x2 */
176 #define CFG_SCLKCNT_MASK 0xFF000000
177 #define CFG_RXBITS(rx) ((rx) << 16) /* 0x1F~0x1 */
178 #define CFG_RXBITS_MASK 0x00FF0000
179 #define CFG_TXBITS(tx) ((tx) << 8) /* 0x1F~0x1 */
180 #define CFG_TXBITS_MASK 0x0000FF00
182 #define CFG_CLKINV_MASK 0x00000080
184 #define CFG_KEEPXFER_MASK 0x00000040
186 #define CFG_RXBITSTO0_MASK 0x00000020
188 #define CFG_TXBITSTO0_MASK 0x00000010
190 #define CFG_SPI_ENA_MASK 0x00000008
192 #define CFG_SPI_SEL_MASK 0x00000004
194 #define CFG_SPI_3W4WB_MASK 0x00000002
196 #define CFG_SPI_START_MASK 0x00000001
199 #define LCD_SPU_SPI_TXDATA 0x0184
205 #define LCD_SPU_SMPN_CTRL 0x0188
207 /* DMA Control 0 Register */
208 #define LCD_SPU_DMA_CTRL0 0x0190
210 #define CFG_NOBLENDING_MASK 0x80000000
212 #define CFG_GAMMA_ENA_MASK 0x40000000
214 #define CFG_CBSH_ENA_MASK 0x20000000
216 #define CFG_PALETTE_ENA_MASK 0x10000000
218 #define CFG_ARBFAST_ENA_MASK 0x08000000
220 #define CFG_HWC_1BITMOD_MASK 0x04000000
222 #define CFG_HWC_1BITENA_MASK 0x02000000
224 #define CFG_HWC_ENA_MASK 0x01000000
226 #define CFG_DMAFORMAT_MASK 0x00F00000
228 #define CFG_GRAFORMAT_MASK 0x000F0000
231 #define CFG_GRA_FTOGGLE_MASK 0x00008000
233 #define CFG_GRA_HSMOOTH_MASK 0x00004000
235 #define CFG_GRA_TSTMODE_MASK 0x00002000
237 #define CFG_GRA_SWAPRB_MASK 0x00001000
239 #define CFG_GRA_SWAPUV_MASK 0x00000800
241 #define CFG_GRA_SWAPYU_MASK 0x00000400
243 #define CFG_YUV2RGB_GRA_MASK 0x00000200
245 #define CFG_GRA_ENA_MASK 0x00000100
248 #define CFG_DMA_FTOGGLE_MASK 0x00000080
250 #define CFG_DMA_HSMOOTH_MASK 0x00000040
252 #define CFG_DMA_TSTMODE_MASK 0x00000020
254 #define CFG_DMA_SWAPRB_MASK 0x00000010
256 #define CFG_DMA_SWAPUV_MASK 0x00000008
258 #define CFG_DMA_SWAPYU_MASK 0x00000004
259 #define CFG_DMA_SWAP_MASK 0x0000001C
261 #define CFG_YUV2RGB_DMA_MASK 0x00000002
263 #define CFG_DMA_ENA_MASK 0x00000001
266 #define LCD_SPU_DMA_CTRL1 0x0194
268 #define CFG_FRAME_TRIG_MASK 0x80000000
270 #define CFG_VSYNC_TRIG_MASK 0x70000000
272 #define CFG_VSYNC_INV_MASK 0x08000000
274 #define CFG_COLOR_KEY_MASK 0x07000000
276 #define CFG_CARRY_MASK 0x00800000
278 #define CFG_LNBUF_ENA_MASK 0x00400000
280 #define CFG_GATED_ENA_MASK 0x00200000
282 #define CFG_PWRDN_ENA_MASK 0x00100000
284 #define CFG_DSCALE_MASK 0x000C0000
286 #define CFG_ALPHA_MODE_MASK 0x00030000
288 #define CFG_ALPHA_MASK 0x0000FF00
290 #define CFG_PXLCMD_MASK 0x000000FF
293 #define LCD_SPU_SRAM_CTRL 0x0198
295 #define CFG_SRAM_INIT_WR_RD_MASK 0x0000C000
297 #define CFG_SRAM_ADDR_LCDID_MASK 0x00000F00
299 #define CFG_SRAM_ADDR_MASK 0x000000FF
302 #define LCD_SPU_SRAM_WRDAT 0x019C
305 #define LCD_SPU_SRAM_PARA0 0x01A0
308 #define LCD_SPU_SRAM_PARA1 0x01A4
310 #define CFG_CSB_256x32_MASK 0x00008000
312 #define CFG_CSB_256x24_MASK 0x00004000
314 #define CFG_CSB_256x8_MASK 0x00002000
316 #define CFG_PDWN256x32_MASK 0x00000080
318 #define CFG_PDWN256x24_MASK 0x00000040
320 #define CFG_PDWN256x8_MASK 0x00000020
322 #define CFG_PDWN32x32_MASK 0x00000008
324 #define CFG_PDWN16x66_MASK 0x00000004
326 #define CFG_PDWN32x66_MASK 0x00000002
328 #define CFG_PDWN64x66_MASK 0x00000001
331 #define LCD_CFG_SCLK_DIV 0x01A8
333 #define SCLK_SOURCE_SELECT_MASK 0x80000000
335 #define CLK_FRACDIV_MASK 0x0FFF0000
337 #define CLK_INT_DIV_MASK 0x0000FFFF
340 #define LCD_SPU_CONTRAST 0x01AC
342 #define CFG_BRIGHTNESS_MASK 0xFFFF0000
344 #define CFG_CONTRAST_MASK 0x0000FFFF
347 #define LCD_SPU_SATURATION 0x01B0
349 #define CFG_C_MULTS_MASK 0xFFFF0000
351 #define CFG_SATURATION_MASK 0x0000FFFF
354 #define LCD_SPU_CBSH_HUE 0x01B4
356 #define CFG_SIN0_MASK 0xFFFF0000
358 #define CFG_COS0_MASK 0x0000FFFF
361 #define LCD_SPU_DUMB_CTRL 0x01B8
363 #define CFG_DUMBMODE_MASK 0xF0000000
365 #define CFG_LCDGPIO_O_MASK 0x0FF00000
367 #define CFG_LCDGPIO_ENA_MASK 0x000FF000
369 #define CFG_BIAS_OUT_MASK 0x00000100
371 #define CFG_REVERSE_RGB_MASK 0x00000080
373 #define CFG_INV_COMPBLANK_MASK 0x00000040
375 #define CFG_INV_COMPSYNC_MASK 0x00000020
377 #define CFG_INV_HENA_MASK 0x00000010
379 #define CFG_INV_VSYNC_MASK 0x00000008
381 #define CFG_INV_HSYNC_MASK 0x00000004
383 #define CFG_INV_PCLK_MASK 0x00000002
385 #define CFG_DUMB_ENA_MASK 0x00000001
388 #define SPU_IOPAD_CONTROL 0x01BC
390 #define CFG_GRA_VM_ENA_MASK 0x00008000
392 #define CFG_DMA_VM_ENA_MASK 0x00002000
394 #define CFG_CMD_VM_ENA_MASK 0x00000800
396 #define CFG_CSC_MASK 0x00000300
398 #define CFG_AXICTRL_MASK 0x000000F0
400 #define CFG_IOPADMODE_MASK 0x0000000F
403 #define SPU_IRQ_ENA 0x01C0
405 #define DMA_FRAME_IRQ0_ENA_MASK 0x80000000
407 #define DMA_FRAME_IRQ1_ENA_MASK 0x40000000
409 #define DMA_FF_UNDERFLOW_ENA_MASK 0x20000000
411 #define GRA_FRAME_IRQ0_ENA_MASK 0x08000000
413 #define GRA_FRAME_IRQ1_ENA_MASK 0x04000000
415 #define GRA_FF_UNDERFLOW_ENA_MASK 0x02000000
417 #define VSYNC_IRQ_ENA_MASK 0x00800000
419 #define DUMB_FRAMEDONE_ENA_MASK 0x00400000
421 #define TWC_FRAMEDONE_ENA_MASK 0x00200000
423 #define HWC_FRAMEDONE_ENA_MASK 0x00100000
425 #define SLV_IRQ_ENA_MASK 0x00080000
427 #define SPI_IRQ_ENA_MASK 0x00040000
429 #define PWRDN_IRQ_ENA_MASK 0x00020000
431 #define ERR_IRQ_ENA_MASK 0x00010000
433 #define CLEAN_SPU_IRQ_ISR_MASK 0x0000FFFF
436 #define SPU_IRQ_ISR 0x01C4
438 #define DMA_FRAME_IRQ0_MASK 0x80000000
440 #define DMA_FRAME_IRQ1_MASK 0x40000000
442 #define DMA_FF_UNDERFLOW_MASK 0x20000000
444 #define GRA_FRAME_IRQ0_MASK 0x08000000
446 #define GRA_FRAME_IRQ1_MASK 0x04000000
448 #define GRA_FF_UNDERFLOW_MASK 0x02000000
450 #define VSYNC_IRQ_MASK 0x00800000
452 #define DUMB_FRAMEDONE_MASK 0x00400000
454 #define TWC_FRAMEDONE_MASK 0x00200000
456 #define HWC_FRAMEDONE_MASK 0x00100000
458 #define SLV_IRQ_MASK 0x00080000
460 #define SPI_IRQ_MASK 0x00040000
462 #define PWRDN_IRQ_MASK 0x00020000
464 #define ERR_IRQ_MASK 0x00010000
466 #define DMA_FRAME_IRQ0_LEVEL_MASK 0x00008000
467 #define DMA_FRAME_IRQ1_LEVEL_MASK 0x00004000
468 #define DMA_FRAME_CNT_ISR_MASK 0x00003000
469 #define GRA_FRAME_IRQ0_LEVEL_MASK 0x00000800
470 #define GRA_FRAME_IRQ1_LEVEL_MASK 0x00000400
471 #define GRA_FRAME_CNT_ISR_MASK 0x00000300
472 #define VSYNC_IRQ_LEVEL_MASK 0x00000080
473 #define DUMB_FRAMEDONE_LEVEL_MASK 0x00000040
474 #define TWC_FRAMEDONE_LEVEL_MASK 0x00000020
475 #define HWC_FRAMEDONE_LEVEL_MASK 0x00000010
476 #define SLV_FF_EMPTY_MASK 0x00000008
477 #define DMA_FF_ALLEMPTY_MASK 0x00000004
478 #define GRA_FF_ALLEMPTY_MASK 0x00000002
479 #define PWRDN_IRQ_LEVEL_MASK 0x00000001
483 * defined Video Memory Color format for DMA control 0 register
486 #define VMODE_RGB565 0x0
487 #define VMODE_RGB1555 0x1
488 #define VMODE_RGB888PACKED 0x2
489 #define VMODE_RGB888UNPACKED 0x3
490 #define VMODE_RGBA888 0x4
491 #define VMODE_YUV422PACKED 0x5
492 #define VMODE_YUV422PLANAR 0x6
493 #define VMODE_YUV420PLANAR 0x7
494 #define VMODE_SMPNCMD 0x8
495 #define VMODE_PALETTE4BIT 0x9
496 #define VMODE_PALETTE8BIT 0xa
497 #define VMODE_RESERVED 0xb
500 * defined Graphic Memory Color format for DMA control 0 register
503 #define GMODE_RGB565 0x0
504 #define GMODE_RGB1555 0x1
505 #define GMODE_RGB888PACKED 0x2
506 #define GMODE_RGB888UNPACKED 0x3
507 #define GMODE_RGBA888 0x4
508 #define GMODE_YUV422PACKED 0x5
509 #define GMODE_YUV422PLANAR 0x6
510 #define GMODE_YUV420PLANAR 0x7
511 #define GMODE_SMPNCMD 0x8
512 #define GMODE_PALETTE4BIT 0x9
513 #define GMODE_PALETTE8BIT 0xa
514 #define GMODE_RESERVED 0xb
536 #define DUMB16_RGB565_0 0x0
537 #define DUMB16_RGB565_1 0x1
538 #define DUMB18_RGB666_0 0x2
539 #define DUMB18_RGB666_1 0x3
540 #define DUMB12_RGB444_0 0x4
541 #define DUMB12_RGB444_1 0x5
542 #define DUMB24_RGB888_0 0x6
543 #define DUMB_BLANK 0x7
547 * LCD LCD I/O Pads control register bit[3:0]
549 #define IOPAD_DUMB24 0x0
550 #define IOPAD_DUMB18SPI 0x1
551 #define IOPAD_DUMB18GPIO 0x2
552 #define IOPAD_DUMB16SPI 0x3
553 #define IOPAD_DUMB16GPIO 0x4
554 #define IOPAD_DUMB12 0x5
555 #define IOPAD_SMART18SPI 0x6
556 #define IOPAD_SMART16SPI 0x7
557 #define IOPAD_SMART8BOTH 0x8