129 	out_min = out_min ? out_min : 1;  in dss_pll_hsdiv_calc()
132 	m_start = max(DIV_ROUND_UP(clkdco, out_max), 1ul);  in dss_pll_hsdiv_calc()
162 	n_start = max(DIV_ROUND_UP(clkin, fint_hw_max), 1ul);  in dss_pll_calc()
171 				1ul);  in dss_pll_calc()
200 	/* then loop for 500ms, sleeping for 1ms in between */  in wait_for_bit_change()
218 	if (wait_for_bit_change(base + PLL_STATUS, 0, 1) != 1)  in dss_pll_wait_reset_done()
244 	u32 l;  in dss_pll_write_config_type_a()  local
246 	l = 0;  in dss_pll_write_config_type_a()
248 		l = FLD_MOD(l, 1, 0, 0);		/* PLL_STOPMODE */  in dss_pll_write_config_type_a()
249 	l = FLD_MOD(l, cinfo->n - 1, hw->n_msb, hw->n_lsb);	/* PLL_REGN */  in dss_pll_write_config_type_a()
250 	l = FLD_MOD(l, cinfo->m, hw->m_msb, hw->m_lsb);		/* PLL_REGM */  in dss_pll_write_config_type_a()
252 	l = FLD_MOD(l, cinfo->mX[0] ? cinfo->mX[0] - 1 : 0,  in dss_pll_write_config_type_a()
255 	l = FLD_MOD(l, cinfo->mX[1] ? cinfo->mX[1] - 1 : 0,  in dss_pll_write_config_type_a()
256 			hw->mX_msb[1], hw->mX_lsb[1]);  in dss_pll_write_config_type_a()
257 	writel_relaxed(l, base + PLL_CONFIGURATION1);  in dss_pll_write_config_type_a()
259 	l = 0;  in dss_pll_write_config_type_a()
261 	l = FLD_MOD(l, cinfo->mX[2] ? cinfo->mX[2] - 1 : 0,  in dss_pll_write_config_type_a()
264 	l = FLD_MOD(l, cinfo->mX[3] ? cinfo->mX[3] - 1 : 0,  in dss_pll_write_config_type_a()
266 	writel_relaxed(l, base + PLL_CONFIGURATION3);  in dss_pll_write_config_type_a()
268 	l = readl_relaxed(base + PLL_CONFIGURATION2);  in dss_pll_write_config_type_a()
276 		l = FLD_MOD(l, f, 4, 1);	/* PLL_FREQSEL */  in dss_pll_write_config_type_a()
280 		l = FLD_MOD(l, f, 3, 1);	/* PLL_SELFREQDCO */  in dss_pll_write_config_type_a()
282 	l = FLD_MOD(l, 1, 13, 13);		/* PLL_REFEN */  in dss_pll_write_config_type_a()
283 	l = FLD_MOD(l, 0, 14, 14);		/* PHY_CLKINEN */  in dss_pll_write_config_type_a()
284 	l = FLD_MOD(l, 0, 16, 16);		/* M4_CLOCK_EN */  in dss_pll_write_config_type_a()
285 	l = FLD_MOD(l, 0, 18, 18);		/* M5_CLOCK_EN */  in dss_pll_write_config_type_a()
286 	l = FLD_MOD(l, 1, 20, 20);		/* HSDIVBYPASS */  in dss_pll_write_config_type_a()
288 		l = FLD_MOD(l, 3, 22, 21);	/* REFSEL = sysclk */  in dss_pll_write_config_type_a()
289 	l = FLD_MOD(l, 0, 23, 23);		/* M6_CLOCK_EN */  in dss_pll_write_config_type_a()
290 	l = FLD_MOD(l, 0, 25, 25);		/* M7_CLOCK_EN */  in dss_pll_write_config_type_a()
291 	writel_relaxed(l, base + PLL_CONFIGURATION2);  in dss_pll_write_config_type_a()
293 	writel_relaxed(1, base + PLL_GO);	/* PLL_GO */  in dss_pll_write_config_type_a()
301 	if (wait_for_bit_change(base + PLL_STATUS, 1, 1) != 1) {  in dss_pll_write_config_type_a()
307 	l = readl_relaxed(base + PLL_CONFIGURATION2);  in dss_pll_write_config_type_a()
308 	l = FLD_MOD(l, 1, 14, 14);			/* PHY_CLKINEN */  in dss_pll_write_config_type_a()
309 	l = FLD_MOD(l, cinfo->mX[0] ? 1 : 0, 16, 16);	/* M4_CLOCK_EN */  in dss_pll_write_config_type_a()
310 	l = FLD_MOD(l, cinfo->mX[1] ? 1 : 0, 18, 18);	/* M5_CLOCK_EN */  in dss_pll_write_config_type_a()
311 	l = FLD_MOD(l, 0, 20, 20);			/* HSDIVBYPASS */  in dss_pll_write_config_type_a()
312 	l = FLD_MOD(l, cinfo->mX[2] ? 1 : 0, 23, 23);	/* M6_CLOCK_EN */  in dss_pll_write_config_type_a()
313 	l = FLD_MOD(l, cinfo->mX[3] ? 1 : 0, 25, 25);	/* M7_CLOCK_EN */  in dss_pll_write_config_type_a()
314 	writel_relaxed(l, base + PLL_CONFIGURATION2);  in dss_pll_write_config_type_a()
318 		(cinfo->mX[1] ? BIT(8) : 0) |  in dss_pll_write_config_type_a()
335 	u32 l;  in dss_pll_write_config_type_b()  local
337 	l = 0;  in dss_pll_write_config_type_b()
338 	l = FLD_MOD(l, cinfo->m, 20, 9);	/* PLL_REGM */  in dss_pll_write_config_type_b()
339 	l = FLD_MOD(l, cinfo->n - 1, 8, 1);	/* PLL_REGN */  in dss_pll_write_config_type_b()
340 	writel_relaxed(l, base + PLL_CONFIGURATION1);  in dss_pll_write_config_type_b()
342 	l = readl_relaxed(base + PLL_CONFIGURATION2);  in dss_pll_write_config_type_b()
343 	l = FLD_MOD(l, 0x0, 12, 12);	/* PLL_HIGHFREQ divide by 2 */  in dss_pll_write_config_type_b()
344 	l = FLD_MOD(l, 0x1, 13, 13);	/* PLL_REFEN */  in dss_pll_write_config_type_b()
345 	l = FLD_MOD(l, 0x0, 14, 14);	/* PHY_CLKINEN */  in dss_pll_write_config_type_b()
347 		l = FLD_MOD(l, 0x3, 22, 21);	/* REFSEL = SYSCLK */  in dss_pll_write_config_type_b()
351 		l = FLD_MOD(l, 0x4, 3, 1);  in dss_pll_write_config_type_b()
353 		l = FLD_MOD(l, 0x2, 3, 1);  in dss_pll_write_config_type_b()
354 	writel_relaxed(l, base + PLL_CONFIGURATION2);  in dss_pll_write_config_type_b()
356 	l = readl_relaxed(base + PLL_CONFIGURATION3);  in dss_pll_write_config_type_b()
357 	l = FLD_MOD(l, cinfo->sd, 17, 10);	/* PLL_REGSD */  in dss_pll_write_config_type_b()
358 	writel_relaxed(l, base + PLL_CONFIGURATION3);  in dss_pll_write_config_type_b()
360 	l = readl_relaxed(base + PLL_CONFIGURATION4);  in dss_pll_write_config_type_b()
361 	l = FLD_MOD(l, cinfo->mX[0], 24, 18);	/* PLL_REGM2 */  in dss_pll_write_config_type_b()
362 	l = FLD_MOD(l, cinfo->mf, 17, 0);	/* PLL_REGM_F */  in dss_pll_write_config_type_b()
363 	writel_relaxed(l, base + PLL_CONFIGURATION4);  in dss_pll_write_config_type_b()
365 	writel_relaxed(1, base + PLL_GO);	/* PLL_GO */  in dss_pll_write_config_type_b()
372 	if (wait_for_bit_change(base + PLL_STATUS, 1, 1) != 1) {  in dss_pll_write_config_type_b()