21 void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s)  in hdmi_wp_dump()  argument
23 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, hdmi_read_reg(wp->base, r))  in hdmi_wp_dump()
45 u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp)  in hdmi_wp_get_irqstatus()  argument
47 	return hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS);  in hdmi_wp_get_irqstatus()
50 void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus)  in hdmi_wp_set_irqstatus()  argument
52 	hdmi_write_reg(wp->base, HDMI_WP_IRQSTATUS, irqstatus);  in hdmi_wp_set_irqstatus()
54 	hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS);  in hdmi_wp_set_irqstatus()
57 void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask)  in hdmi_wp_set_irqenable()  argument
59 	hdmi_write_reg(wp->base, HDMI_WP_IRQENABLE_SET, mask);  in hdmi_wp_set_irqenable()
62 void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask)  in hdmi_wp_clear_irqenable()  argument
64 	hdmi_write_reg(wp->base, HDMI_WP_IRQENABLE_CLR, mask);  in hdmi_wp_clear_irqenable()
68 int hdmi_wp_set_phy_pwr(struct hdmi_wp_data *wp, enum hdmi_phy_pwr val)  in hdmi_wp_set_phy_pwr()  argument
71 	if (REG_GET(wp->base, HDMI_WP_PWR_CTRL, 5, 4) == val)  in hdmi_wp_set_phy_pwr()
75 	REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 7, 6);  in hdmi_wp_set_phy_pwr()
78 	if (hdmi_wait_for_bit_change(wp->base, HDMI_WP_PWR_CTRL, 5, 4, val)  in hdmi_wp_set_phy_pwr()
88 int hdmi_wp_set_pll_pwr(struct hdmi_wp_data *wp, enum hdmi_pll_pwr val)  in hdmi_wp_set_pll_pwr()  argument
91 	REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 3, 2);  in hdmi_wp_set_pll_pwr()
94 	if (hdmi_wait_for_bit_change(wp->base, HDMI_WP_PWR_CTRL, 1, 0, val)  in hdmi_wp_set_pll_pwr()
103 int hdmi_wp_video_start(struct hdmi_wp_data *wp)  in hdmi_wp_video_start()  argument
105 	REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, true, 31, 31);  in hdmi_wp_video_start()
110 void hdmi_wp_video_stop(struct hdmi_wp_data *wp)  in hdmi_wp_video_stop()  argument
114 	hdmi_write_reg(wp->base, HDMI_WP_IRQSTATUS, HDMI_IRQ_VIDEO_FRAME_DONE);  in hdmi_wp_video_stop()
116 	REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, false, 31, 31);  in hdmi_wp_video_stop()
123 		v = hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS_RAW);  in hdmi_wp_video_stop()
131 void hdmi_wp_video_config_format(struct hdmi_wp_data *wp,  in hdmi_wp_video_config_format()  argument
136 	REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, video_fmt->packing_mode,  in hdmi_wp_video_config_format()
141 	hdmi_write_reg(wp->base, HDMI_WP_VIDEO_SIZE, l);  in hdmi_wp_video_config_format()
144 void hdmi_wp_video_config_interface(struct hdmi_wp_data *wp,  in hdmi_wp_video_config_interface()  argument
154 	r = hdmi_read_reg(wp->base, HDMI_WP_VIDEO_CFG);  in hdmi_wp_video_config_interface()
159 	hdmi_write_reg(wp->base, HDMI_WP_VIDEO_CFG, r);  in hdmi_wp_video_config_interface()
162 void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp,  in hdmi_wp_video_config_timing()  argument
173 	hdmi_write_reg(wp->base, HDMI_WP_VIDEO_TIMING_H, timing_h);  in hdmi_wp_video_config_timing()
178 	hdmi_write_reg(wp->base, HDMI_WP_VIDEO_TIMING_V, timing_v);  in hdmi_wp_video_config_timing()
203 void hdmi_wp_audio_config_format(struct hdmi_wp_data *wp,  in hdmi_wp_audio_config_format()  argument
210 	r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CFG);  in hdmi_wp_audio_config_format()
223 	hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CFG, r);  in hdmi_wp_audio_config_format()
226 void hdmi_wp_audio_config_dma(struct hdmi_wp_data *wp,  in hdmi_wp_audio_config_dma()  argument
233 	r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CFG2);  in hdmi_wp_audio_config_dma()
236 	hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CFG2, r);  in hdmi_wp_audio_config_dma()
238 	r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CTRL);  in hdmi_wp_audio_config_dma()
241 	hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CTRL, r);  in hdmi_wp_audio_config_dma()
244 int hdmi_wp_audio_enable(struct hdmi_wp_data *wp, bool enable)  in hdmi_wp_audio_enable()  argument
246 	REG_FLD_MOD(wp->base, HDMI_WP_AUDIO_CTRL, enable, 31, 31);  in hdmi_wp_audio_enable()
251 int hdmi_wp_audio_core_req_enable(struct hdmi_wp_data *wp, bool enable)  in hdmi_wp_audio_core_req_enable()  argument
253 	REG_FLD_MOD(wp->base, HDMI_WP_AUDIO_CTRL, enable, 30, 30);  in hdmi_wp_audio_core_req_enable()
258 int hdmi_wp_init(struct platform_device *pdev, struct hdmi_wp_data *wp)  in hdmi_wp_init()  argument
262 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "wp");  in hdmi_wp_init()
264 		DSSERR("can't get WP mem resource\n");  in hdmi_wp_init()
267 	wp->phys_base = res->start;  in hdmi_wp_init()
269 	wp->base = devm_ioremap_resource(&pdev->dev, res);  in hdmi_wp_init()
270 	if (IS_ERR(wp->base)) {  in hdmi_wp_init()
271 		DSSERR("can't ioremap HDMI WP\n");  in hdmi_wp_init()
272 		return PTR_ERR(wp->base);  in hdmi_wp_init()
278 phys_addr_t hdmi_wp_get_audio_dma_addr(struct hdmi_wp_data *wp)  in hdmi_wp_get_audio_dma_addr()  argument
280 	return wp->phys_base + HDMI_WP_AUDIO_DATA;  in hdmi_wp_get_audio_dma_addr()