1 // SPDX-License-Identifier: GPL-2.0-only
25 #define DUMPPLL(r) seq_printf(s, "%-35s %08x\n", #r,\  in hdmi_pll_dump()
26 		hdmi_read_reg(pll->base, r))  in hdmi_pll_dump()
47 	const struct dss_pll_hw *hw = pll->pll.hw;  in hdmi_pll_compute()
49 	clkin = clk_get_rate(pll->pll.clkin);  in hdmi_pll_compute()
56 	n = DIV_ROUND_UP(clkin, hw->fint_max);  in hdmi_pll_compute()
60 	min_dco = roundup(hw->clkdco_min, fint);  in hdmi_pll_compute()
71 	if (WARN_ON(target_clkdco - clkdco > fint))  in hdmi_pll_compute()
74 		mf = (u32)div_u64(262144ull * (target_clkdco - clkdco), fint);  in hdmi_pll_compute()
81 	/* sigma-delta */  in hdmi_pll_compute()
88 	pi->n = n;  in hdmi_pll_compute()
89 	pi->m = m;  in hdmi_pll_compute()
90 	pi->mf = mf;  in hdmi_pll_compute()
91 	pi->mX[0] = m2;  in hdmi_pll_compute()
92 	pi->sd = sd;  in hdmi_pll_compute()
94 	pi->fint = fint;  in hdmi_pll_compute()
95 	pi->clkdco = clkdco;  in hdmi_pll_compute()
96 	pi->clkout[0] = clkout;  in hdmi_pll_compute()
102 	struct hdmi_wp_data *wp = pll->wp;  in hdmi_pll_enable()
112 	struct hdmi_wp_data *wp = pll->wp;  in hdmi_pll_disable()
174 	struct dss_pll *pll = &hpll->pll;  in dsi_init_pll_data()
177 	clk = devm_clk_get(&pdev->dev, "sys_clk");  in dsi_init_pll_data()
183 	pll->name = "hdmi";  in dsi_init_pll_data()
184 	pll->id = DSS_PLL_HDMI;  in dsi_init_pll_data()
185 	pll->base = hpll->base;  in dsi_init_pll_data()
186 	pll->clkin = clk;  in dsi_init_pll_data()
192 		pll->hw = &dss_omap4_hdmi_pll_hw;  in dsi_init_pll_data()
197 		pll->hw = &dss_omap5_hdmi_pll_hw;  in dsi_init_pll_data()
201 		return -ENODEV;  in dsi_init_pll_data()
204 	pll->ops = &dsi_pll_ops;  in dsi_init_pll_data()
213 	pll->wp = wp;  in hdmi_pll_init()
215 	pll->base = devm_platform_ioremap_resource_byname(pdev, "pll");  in hdmi_pll_init()
216 	if (IS_ERR(pll->base)) {  in hdmi_pll_init()
218 		return PTR_ERR(pll->base);  in hdmi_pll_init()
232 	struct dss_pll *pll = &hpll->pll;  in hdmi_pll_uninit()