Lines Matching refs:dsi_write_reg
115 dsi_write_reg(dsidev, idx, FLD_MOD(dsi_read_reg(dsidev, idx), val, start, end))
432 static inline void dsi_write_reg(struct platform_device *dsidev, in dsi_write_reg() function
809 dsi_write_reg(dsidev, DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK); in omap_dsi_irq_handler()
821 dsi_write_reg(dsidev, DSI_VC_IRQSTATUS(i), vcstatus[i]); in omap_dsi_irq_handler()
829 dsi_write_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS, ciostatus); in omap_dsi_irq_handler()
882 dsi_write_reg(dsidev, status_reg, (mask ^ old_mask) & mask); in _omap_dsi_configure_irqs()
883 dsi_write_reg(dsidev, enable_reg, mask); in _omap_dsi_configure_irqs()
1850 dsi_write_reg(dsidev, DSI_COMPLEXIO_CFG1, r); in dsi_set_lane_config()
1929 dsi_write_reg(dsidev, DSI_DSIPHY_CFG0, r); in dsi_cio_timings()
1942 dsi_write_reg(dsidev, DSI_DSIPHY_CFG1, r); in dsi_cio_timings()
1946 dsi_write_reg(dsidev, DSI_DSIPHY_CFG2, r); in dsi_cio_timings()
2097 dsi_write_reg(dsidev, DSI_TIMING1, l); in dsi_cio_init()
2226 dsi_write_reg(dsidev, DSI_TX_FIFO_VC_SIZE, r); in dsi_config_tx_fifo()
2259 dsi_write_reg(dsidev, DSI_RX_FIFO_VC_SIZE, r); in dsi_config_rx_fifo()
2268 dsi_write_reg(dsidev, DSI_TIMING1, r); in dsi_force_tx_stop_mode_io()
2445 dsi_write_reg(dsidev, DSI_VC_CTRL(channel), r); in dsi_vc_initial_config()
2672 dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_HEADER(channel), val); in dsi_vc_write_long_header()
2685 dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_PAYLOAD(channel), val); in dsi_vc_write_long_payload()
2777 dsi_write_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel), r); in dsi_vc_send_short()
3223 dsi_write_reg(dsidev, DSI_TIMING2, r); in dsi_set_lp_rx_timeout()
3250 dsi_write_reg(dsidev, DSI_TIMING1, r); in dsi_set_ta_timeout()
3277 dsi_write_reg(dsidev, DSI_TIMING1, r); in dsi_set_stop_state_counter()
3304 dsi_write_reg(dsidev, DSI_TIMING2, r); in dsi_set_hs_tx_timeout()
3358 dsi_write_reg(dsidev, DSI_CTRL, r); in dsi_config_vp_sync_events()
3379 dsi_write_reg(dsidev, DSI_CTRL, r); in dsi_config_blanking_modes()
3547 dsi_write_reg(dsidev, DSI_VM_TIMING4, r); in dsi_config_cmd_mode_interleaving()
3553 dsi_write_reg(dsidev, DSI_VM_TIMING5, r); in dsi_config_cmd_mode_interleaving()
3558 dsi_write_reg(dsidev, DSI_VM_TIMING6, r); in dsi_config_cmd_mode_interleaving()
3613 dsi_write_reg(dsidev, DSI_CTRL, r); in dsi_proto_config()
3675 dsi_write_reg(dsidev, DSI_CLK_TIMING, r); in dsi_proto_timings()
3689 dsi_write_reg(dsidev, DSI_VM_TIMING7, r); in dsi_proto_timings()
3727 dsi_write_reg(dsidev, DSI_VM_TIMING1, r); in dsi_proto_timings()
3734 dsi_write_reg(dsidev, DSI_VM_TIMING2, r); in dsi_proto_timings()
3739 dsi_write_reg(dsidev, DSI_VM_TIMING3, r); in dsi_proto_timings()
3943 dsi_write_reg(dsidev, DSI_VC_TE(channel), l); in dsi_update_screen_dispc()
3952 dsi_write_reg(dsidev, DSI_VC_TE(channel), l); in dsi_update_screen_dispc()