127 } dispc;  variable
253 	__raw_writel(val, dispc.base + idx);  in dispc_write_reg()
258 	return __raw_readl(dispc.base + idx);  in dispc_read_reg()
274 		spin_lock_irqsave(&dispc.control_lock, flags);  in mgr_fld_write()
279 		spin_unlock_irqrestore(&dispc.control_lock, flags);  in mgr_fld_write()
283 	dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
285 	dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
389 	dispc.ctx_valid = true;  in dispc_save_context()
400 	if (!dispc.ctx_valid)  in dispc_restore_context()
522 	r = pm_runtime_resume_and_get(&dispc.pdev->dev);  in dispc_runtime_get()
535 	r = pm_runtime_put_sync(&dispc.pdev->dev);  in dispc_runtime_put()
548 	if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc.feat->no_framedone_tv)  in dispc_mgr_get_framedone_irq()
693 	if (dispc.feat->has_writeback)  in dispc_setup_color_conv_coef()
1021 	if (dispc.feat->has_writeback)  in dispc_configure_burst_sizes()
1103 	val = FLD_VAL(height - 1, dispc.feat->mgr_height_start, 16) |  in dispc_mgr_set_size()
1104 		FLD_VAL(width - 1, dispc.feat->mgr_width_start, 0);  in dispc_mgr_set_size()
1121 	for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {  in dispc_init_fifos()
1124 		dispc.fifo_size[fifo] = size;  in dispc_init_fifos()
1130 		dispc.fifo_assignment[fifo] = fifo;  in dispc_init_fifos()
1140 	if (dispc.feat->gfx_fifo_workaround) {  in dispc_init_fifos()
1152 		dispc.fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB;  in dispc_init_fifos()
1153 		dispc.fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX;  in dispc_init_fifos()
1170 	if (dispc.feat->has_writeback) {  in dispc_init_fifos()
1187 	for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {  in dispc_ovl_get_fifo_size()
1188 		if (dispc.fifo_assignment[fifo] == plane)  in dispc_ovl_get_fifo_size()
1189 			size += dispc.fifo_size[fifo];  in dispc_ovl_get_fifo_size()
1228 	if (dss_has_feature(FEAT_PRELOAD) && dispc.feat->set_max_preload &&  in dispc_ovl_set_fifo_threshold()
1347 	if (dispc.feat->has_writeback) {  in dispc_init_mflag()
2267 		*core_clk = dispc.feat->calc_core_clk(pclk, in_width,  in dispc_ovl_calc_scaling_24xx()
2322 			*core_clk = dispc.feat->calc_core_clk(pclk, in_width,  in dispc_ovl_calc_scaling_34xx()
2417 	*core_clk = dispc.feat->calc_core_clk(pclk, in_width, in_height,  in dispc_ovl_calc_scaling_44xx()
2477 	ret = dispc.feat->calc_scaling(pclk, lclk, mgr_timings, width, height,  in dispc_ovl_calc_scaling()
2714 	if (dispc.feat->last_pixel_inc_missing)  in dispc_ovl_setup_common()
2969 	return width <= dispc.feat->mgr_width_max &&  in _dispc_mgr_size_ok()
2970 		height <= dispc.feat->mgr_height_max;  in _dispc_mgr_size_ok()
2976 	if (hsw < 1 || hsw > dispc.feat->sw_max ||  in _dispc_lcd_timings_ok()
2977 			hfp < 1 || hfp > dispc.feat->hp_max ||  in _dispc_lcd_timings_ok()
2978 			hbp < 1 || hbp > dispc.feat->hp_max ||  in _dispc_lcd_timings_ok()
2979 			vsw < 1 || vsw > dispc.feat->sw_max ||  in _dispc_lcd_timings_ok()
2980 			vfp < 0 || vfp > dispc.feat->vp_max ||  in _dispc_lcd_timings_ok()
2981 			vbp < 0 || vbp > dispc.feat->vp_max)  in _dispc_lcd_timings_ok()
2990 		return pclk <= dispc.feat->max_lcd_pclk;  in _dispc_mgr_pclk_ok()
2992 		return pclk <= dispc.feat->max_tv_pclk;  in _dispc_mgr_pclk_ok()
3030 	timing_h = FLD_VAL(hsw-1, dispc.feat->sw_start, 0) |  in _dispc_mgr_set_lcd_timings()
3031 			FLD_VAL(hfp-1, dispc.feat->fp_start, 8) |  in _dispc_mgr_set_lcd_timings()
3032 			FLD_VAL(hbp-1, dispc.feat->bp_start, 20);  in _dispc_mgr_set_lcd_timings()
3033 	timing_v = FLD_VAL(vsw-1, dispc.feat->sw_start, 0) |  in _dispc_mgr_set_lcd_timings()
3034 			FLD_VAL(vfp, dispc.feat->fp_start, 8) |  in _dispc_mgr_set_lcd_timings()
3035 			FLD_VAL(vbp, dispc.feat->bp_start, 20);  in _dispc_mgr_set_lcd_timings()
3106 	if (dispc.feat->supports_sync_align)  in _dispc_mgr_set_lcd_timings()
3111 	if (dispc.syscon_pol) {  in _dispc_mgr_set_lcd_timings()
3126 		regmap_update_bits(dispc.syscon_pol, dispc.syscon_pol_offset,  in _dispc_mgr_set_lcd_timings()
3185 		dispc.core_clk_rate = dispc_fclk_rate() / lck_div;  in dispc_mgr_set_lcd_divisor()
3285 		return dispc.tv_pclk_rate;  in dispc_mgr_pclk_rate()
3291 	dispc.tv_pclk_rate = pclk;  in dispc_set_tv_pclk()
3296 	return dispc.core_clk_rate;  in dispc_core_clk_rate()
3501 	if (dispc.feat->has_writeback) {  in dispc_dump_regs()
3590 bool dispc_div_calc(unsigned long dispc,  in dispc_div_calc()  argument
3616 	lckd_start = max(DIV_ROUND_UP(dispc, lck_max), 1ul);  in dispc_div_calc()
3617 	lckd_stop = min(dispc / pck_min, 255ul);  in dispc_div_calc()
3620 		lck = dispc / lckd;  in dispc_div_calc()
3726 		dispc.core_clk_rate = dispc_fclk_rate();  in _omap_dispc_initial_config()
3743 	if (dispc.feat->mstandby_workaround)  in _omap_dispc_initial_config()
3888 	if (!dispc.is_enabled)  in dispc_irq_handler()
3891 	return dispc.user_handler(irq, dispc.user_data);  in dispc_irq_handler()
3898 	if (dispc.user_handler != NULL)  in dispc_request_irq()
3901 	dispc.user_handler = handler;  in dispc_request_irq()
3902 	dispc.user_data = dev_id;  in dispc_request_irq()
3907 	r = devm_request_irq(&dispc.pdev->dev, dispc.irq, dispc_irq_handler,  in dispc_request_irq()
3908 			     IRQF_SHARED, "OMAP DISPC", &dispc);  in dispc_request_irq()
3910 		dispc.user_handler = NULL;  in dispc_request_irq()
3911 		dispc.user_data = NULL;  in dispc_request_irq()
3920 	devm_free_irq(&dispc.pdev->dev, dispc.irq, &dispc);  in dispc_free_irq()
3922 	dispc.user_handler = NULL;  in dispc_free_irq()
3923 	dispc.user_data = NULL;  in dispc_free_irq()
3936 	dispc.pdev = pdev;  in dispc_bind()
3938 	spin_lock_init(&dispc.control_lock);  in dispc_bind()
3940 	dispc.feat = dispc_get_features();  in dispc_bind()
3941 	if (!dispc.feat)  in dispc_bind()
3944 	dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);  in dispc_bind()
3950 	dispc.base = devm_ioremap(&pdev->dev, dispc_mem->start,  in dispc_bind()
3952 	if (!dispc.base) {  in dispc_bind()
3957 	dispc.irq = platform_get_irq(dispc.pdev, 0);  in dispc_bind()
3958 	if (dispc.irq < 0) {  in dispc_bind()
3964 		dispc.syscon_pol = syscon_regmap_lookup_by_phandle(np, "syscon-pol");  in dispc_bind()
3965 		if (IS_ERR(dispc.syscon_pol)) {  in dispc_bind()
3967 			return PTR_ERR(dispc.syscon_pol);  in dispc_bind()
3971 				&dispc.syscon_pol_offset)) {  in dispc_bind()
4027 	dispc.is_enabled = false;  in dispc_runtime_suspend()
4031 	synchronize_irq(dispc.irq);  in dispc_runtime_suspend()
4052 	dispc.is_enabled = true;  in dispc_runtime_resume()