56 } dispc_compat;  variable
65 	spin_lock_irqsave(&dispc_compat.irq_stats_lock, flags);  in dispc_dump_irqs()
67 	stats = dispc_compat.irq_stats;  in dispc_dump_irqs()
68 	memset(&dispc_compat.irq_stats, 0, sizeof(dispc_compat.irq_stats));  in dispc_dump_irqs()
69 	dispc_compat.irq_stats.last_reset = jiffies;  in dispc_dump_irqs()
71 	spin_unlock_irqrestore(&dispc_compat.irq_stats_lock, flags);  in dispc_dump_irqs()
124 	mask = dispc_compat.irq_error_mask;  in _omap_dispc_set_irqs()
127 		isr_data = &dispc_compat.registered_isr[i];  in _omap_dispc_set_irqs()
148 	spin_lock_irqsave(&dispc_compat.irq_lock, flags);  in omap_dispc_register_isr()
152 		isr_data = &dispc_compat.registered_isr[i];  in omap_dispc_register_isr()
164 		isr_data = &dispc_compat.registered_isr[i];  in omap_dispc_register_isr()
182 	spin_unlock_irqrestore(&dispc_compat.irq_lock, flags);  in omap_dispc_register_isr()
186 	spin_unlock_irqrestore(&dispc_compat.irq_lock, flags);  in omap_dispc_register_isr()
199 	spin_lock_irqsave(&dispc_compat.irq_lock, flags);  in omap_dispc_unregister_isr()
202 		isr_data = &dispc_compat.registered_isr[i];  in omap_dispc_unregister_isr()
220 	spin_unlock_irqrestore(&dispc_compat.irq_lock, flags);  in omap_dispc_unregister_isr()
228 	if ((status & dispc_compat.irq_error_mask) == 0)  in print_irq_status()
260 	spin_lock(&dispc_compat.irq_lock);  in omap_dispc_irq_handler()
267 		spin_unlock(&dispc_compat.irq_lock);  in omap_dispc_irq_handler()
272 	spin_lock(&dispc_compat.irq_stats_lock);  in omap_dispc_irq_handler()
273 	dispc_compat.irq_stats.irq_count++;  in omap_dispc_irq_handler()
274 	dss_collect_irq_stats(irqstatus, dispc_compat.irq_stats.irqs);  in omap_dispc_irq_handler()
275 	spin_unlock(&dispc_compat.irq_stats_lock);  in omap_dispc_irq_handler()
288 	memcpy(registered_isr, dispc_compat.registered_isr,  in omap_dispc_irq_handler()
291 	spin_unlock(&dispc_compat.irq_lock);  in omap_dispc_irq_handler()
305 	spin_lock(&dispc_compat.irq_lock);  in omap_dispc_irq_handler()
307 	unhandled_errors = irqstatus & ~handledirqs & dispc_compat.irq_error_mask;  in omap_dispc_irq_handler()
310 		dispc_compat.error_irqs |= unhandled_errors;  in omap_dispc_irq_handler()
312 		dispc_compat.irq_error_mask &= ~unhandled_errors;  in omap_dispc_irq_handler()
315 		schedule_work(&dispc_compat.error_work);  in omap_dispc_irq_handler()
318 	spin_unlock(&dispc_compat.irq_lock);  in omap_dispc_irq_handler()
335 	spin_lock_irqsave(&dispc_compat.irq_lock, flags);  in dispc_error_worker()
336 	errors = dispc_compat.error_irqs;  in dispc_error_worker()
337 	dispc_compat.error_irqs = 0;  in dispc_error_worker()
338 	spin_unlock_irqrestore(&dispc_compat.irq_lock, flags);  in dispc_error_worker()
396 	spin_lock_irqsave(&dispc_compat.irq_lock, flags);  in dispc_error_worker()
397 	dispc_compat.irq_error_mask |= errors;  in dispc_error_worker()
399 	spin_unlock_irqrestore(&dispc_compat.irq_lock, flags);  in dispc_error_worker()
409 	spin_lock_init(&dispc_compat.irq_stats_lock);  in dss_dispc_initialize_irq()
410 	dispc_compat.irq_stats.last_reset = jiffies;  in dss_dispc_initialize_irq()
414 	spin_lock_init(&dispc_compat.irq_lock);  in dss_dispc_initialize_irq()
416 	memset(dispc_compat.registered_isr, 0,  in dss_dispc_initialize_irq()
417 			sizeof(dispc_compat.registered_isr));  in dss_dispc_initialize_irq()
419 	dispc_compat.irq_error_mask = DISPC_IRQ_MASK_ERROR;  in dss_dispc_initialize_irq()
421 		dispc_compat.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;  in dss_dispc_initialize_irq()
423 		dispc_compat.irq_error_mask |= DISPC_IRQ_SYNC_LOST3;  in dss_dispc_initialize_irq()
425 		dispc_compat.irq_error_mask |= DISPC_IRQ_VID3_FIFO_UNDERFLOW;  in dss_dispc_initialize_irq()
433 	INIT_WORK(&dispc_compat.error_work, dispc_error_worker);  in dss_dispc_initialize_irq()
437 	r = dispc_request_irq(omap_dispc_irq_handler, &dispc_compat);  in dss_dispc_initialize_irq()
448 	dispc_free_irq(&dispc_compat);  in dss_dispc_uninitialize_irq()