mmp/hw/mmp_ctrl.h

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
16 /* ------------< LCD register >------------ */
150 #define LCD_SCLK(path) ((PATH_PN == path->id) ? LCD_CFG_SCLK_DIV :\
151 	((PATH_TV == path->id) ? LCD_TCLK_DIV : LCD_PN2_SCLK_DIV))
155 /* dither configure */
170 /* dither table data was fixed by video bpp of input and output*/
367 /* I/O Pads Input Read Only Register */
386 #define	 CFG_RXBITS(rx)				(((rx) - 1)<<16) /* 0x1F~0x1 */
388 #define	 CFG_TXBITS(tx)				(((tx) - 1)<<8) /* 0x1F~0x1 */
411    1. Smart Pannel 8-bit Bus Control Register.
439 #define	 CFG_GRA_FTOGGLE(toggle)		((toggle)<<15)  argument
460 #define	 CFG_DMA_FTOGGLE(toggle)		((toggle)<<7)  argument
685 /* FIXME - JUST GUESS */
811 /* read-only */
1016 /* DSI1 - 4 Lane Controller base */
1018 /* DSI2 - 3 Lane Controller base */
1087 /* Rx Packet Header - data from slave device */
1204 /* LCD 1 Input Data RGB Mode for LCD 1 */
1247 /* Time to Drive LP-00 by New Transmitter */
1250 /* Time to Drive LP-00 after Turn Request */
1414 	return overlay->dmafetch_id & 1;  in overlay_is_vid()
1419 	return (struct mmphw_path_plat *)path->plat_data;  in path_to_path_plat()
1424 	return path_to_path_plat(path)->ctrl;  in path_to_ctrl()
1429 	return path_to_ctrl(overlay->path);  in overlay_to_ctrl()
1434 	return path_to_ctrl(path)->reg_base;  in ctrl_regs()
1440 	if (path->id == PATH_PN)  in path_regs()
1442 	else if (path->id == PATH_TV)  in path_regs()
1444 	else if (path->id == PATH_P2)  in path_regs()
1447 		dev_err(path->dev, "path id %d invalid\n", path->id);  in path_regs()