mmp/hw/mmp_ctrl.h

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
16 /* ------------< LCD register >------------ */
150 #define LCD_SCLK(path) ((PATH_PN == path->id) ? LCD_CFG_SCLK_DIV :\
151 	((PATH_TV == path->id) ? LCD_TCLK_DIV : LCD_PN2_SCLK_DIV))
386 #define	 CFG_RXBITS(rx)				(((rx) - 1)<<16) /* 0x1F~0x1 */  argument
388 #define	 CFG_TXBITS(tx)				(((tx) - 1)<<8) /* 0x1F~0x1 */
394 #define	 CFG_RXBITSTO0(rx)			((rx)<<5)  argument
411    1. Smart Pannel 8-bit Bus Control Register.
685 /* FIXME - JUST GUESS */
811 /* read-only */
1015 /* DSI */
1016 /* DSI1 - 4 Lane Controller base */
1018 /* DSI2 - 3 Lane Controller base */
1021 /*	   DSI Controller Registers	   */
1023 #define DSI_LCD1_CTRL_0  0x100   /* DSI Active Panel 1 Control register 0 */
1024 #define DSI_LCD1_CTRL_1  0x104   /* DSI Active Panel 1 Control register 1 */
1055 #define DSI_CTRL_0	  0x000   /* DSI control register 0 */
1056 #define DSI_CTRL_1	  0x004   /* DSI control register 1 */
1064 #define DSI_CPU_CMD_0   0x020   /* DSI CPU packet command register 0 */
1067 #define DSI_CPU_WDAT_0	0x030   /* DSI CUP */
1087 /* Rx Packet Header - data from slave device */
1099 #define DSI_PHY_CTRL_2		0x088   /* DSI DPHI Control Register 2 */
1130 #define DSI_LCD1_CTRL_0  0x100   /* DSI Active Panel 1 Control register 0 */
1131 #define DSI_LCD1_CTRL_1  0x104   /* DSI Active Panel 1 Control register 1 */
1144 #define DSI_LCD2_CTRL_0  0x180   /* DSI Active Panel 2 Control register 0 */
1145 #define DSI_LCD2_CTRL_1  0x184   /* DSI Active Panel 2 Control register 1 */
1154 /*	DSI_CTRL_0		0x0000	DSI Control Register 0 */
1161 /*	DSI_CTRL_1		0x0004	DSI Control Register 1 */
1169 /*	DSI_LCD1_CTRL_1	0x0104	DSI Active Panel 1 Control Register 1 */
1201 /* DSI Transmission Mode for LCD 1 */
1220 /*	DSI_CPU_CMD_1		0x0024	DSI CPU Packet Command Register 1 */
1247 /* Time to Drive LP-00 by New Transmitter */
1250 /* Time to Drive LP-00 after Turn Request */
1414 	return overlay->dmafetch_id & 1;  in overlay_is_vid()
1419 	return (struct mmphw_path_plat *)path->plat_data;  in path_to_path_plat()
1424 	return path_to_path_plat(path)->ctrl;  in path_to_ctrl()
1429 	return path_to_ctrl(overlay->path);  in overlay_to_ctrl()
1434 	return path_to_ctrl(path)->reg_base;  in ctrl_regs()
1440 	if (path->id == PATH_PN)  in path_regs()
1442 	else if (path->id == PATH_TV)  in path_regs()
1444 	else if (path->id == PATH_P2)  in path_regs()
1447 		dev_err(path->dev, "path id %d invalid\n", path->id);  in path_regs()