92 #define TVP3026_INDEX		0x00
93 #define TVP3026_PALWRADD	0x00
94 #define TVP3026_PALDATA		0x01
95 #define TVP3026_PIXRDMSK	0x02
96 #define TVP3026_PALRDADD	0x03
97 #define TVP3026_CURCOLWRADD	0x04
98 #define     TVP3026_CLOVERSCAN		0x00
99 #define     TVP3026_CLCOLOR0		0x01
100 #define     TVP3026_CLCOLOR1		0x02
101 #define     TVP3026_CLCOLOR2		0x03
102 #define TVP3026_CURCOLDATA	0x05
103 #define TVP3026_CURCOLRDADD	0x07
104 #define TVP3026_CURCTRL		0x09
105 #define TVP3026_X_DATAREG	0x0A
106 #define TVP3026_CURRAMDATA	0x0B
107 #define TVP3026_CURPOSXL	0x0C
108 #define TVP3026_CURPOSXH	0x0D
109 #define TVP3026_CURPOSYL	0x0E
110 #define TVP3026_CURPOSYH	0x0F
112 #define TVP3026_XSILICONREV	0x01
113 #define TVP3026_XCURCTRL	0x06
114 #define     TVP3026_XCURCTRL_DIS	0x00	/* transparent, transparent, transparent, transparent */
115 #define     TVP3026_XCURCTRL_3COLOR	0x01	/* transparent, 0, 1, 2 */
116 #define     TVP3026_XCURCTRL_XGA	0x02	/* 0, 1, transparent, complement */
117 #define     TVP3026_XCURCTRL_XWIN	0x03	/* transparent, transparent, 0, 1 */
118 #define     TVP3026_XCURCTRL_BLANK2048	0x00
119 #define     TVP3026_XCURCTRL_BLANK4096	0x10
120 #define     TVP3026_XCURCTRL_INTERLACED	0x20
121 #define     TVP3026_XCURCTRL_ODD	0x00 /* ext.signal ODD/\EVEN */
122 #define     TVP3026_XCURCTRL_EVEN	0x40 /* ext.signal EVEN/\ODD */
123 #define     TVP3026_XCURCTRL_INDIRECT	0x00
124 #define     TVP3026_XCURCTRL_DIRECT	0x80
125 #define TVP3026_XLATCHCTRL	0x0F
126 #define     TVP3026_XLATCHCTRL_1_1	0x06
127 #define     TVP3026_XLATCHCTRL_2_1	0x07
128 #define     TVP3026_XLATCHCTRL_4_1	0x06
129 #define     TVP3026_XLATCHCTRL_8_1	0x06
130 #define     TVP3026_XLATCHCTRL_16_1	0x06
131 #define     TVP3026A_XLATCHCTRL_4_3	0x06	/* ??? do not understand... but it works... !!! */
132 #define     TVP3026A_XLATCHCTRL_8_3	0x07
133 #define     TVP3026B_XLATCHCTRL_4_3	0x08
134 #define     TVP3026B_XLATCHCTRL_8_3	0x06	/* ??? do not understand... but it works... !!! */
135 #define TVP3026_XTRUECOLORCTRL	0x18
136 #define     TVP3026_XTRUECOLORCTRL_VRAM_SHIFT_ACCEL	0x00
137 #define     TVP3026_XTRUECOLORCTRL_VRAM_SHIFT_TVP	0x20
138 #define     TVP3026_XTRUECOLORCTRL_PSEUDOCOLOR		0x80
139 #define     TVP3026_XTRUECOLORCTRL_TRUECOLOR		0x40 /* paletized */
140 #define     TVP3026_XTRUECOLORCTRL_DIRECTCOLOR		0x00
141 #define     TVP3026_XTRUECOLORCTRL_24_ALTERNATE		0x08 /* 5:4/5:2 instead of 4:3/8:3 */
142 #define     TVP3026_XTRUECOLORCTRL_RGB_888		0x16 /* 4:3/8:3 (or 5:4/5:2) */
143 #define	    TVP3026_XTRUECOLORCTRL_BGR_888		0x17
144 #define     TVP3026_XTRUECOLORCTRL_ORGB_8888		0x06
145 #define     TVP3026_XTRUECOLORCTRL_BGRO_8888		0x07
146 #define     TVP3026_XTRUECOLORCTRL_RGB_565		0x05
147 #define     TVP3026_XTRUECOLORCTRL_ORGB_1555		0x04
148 #define     TVP3026_XTRUECOLORCTRL_RGB_664		0x03
149 #define     TVP3026_XTRUECOLORCTRL_RGBO_4444		0x01
150 #define TVP3026_XMUXCTRL	0x19
151 #define     TVP3026_XMUXCTRL_MEMORY_8BIT			0x01 /* - */
152 #define     TVP3026_XMUXCTRL_MEMORY_16BIT			0x02 /* - */
153 #define     TVP3026_XMUXCTRL_MEMORY_32BIT			0x03 /* 2MB RAM, 512K * 4 */
154 #define     TVP3026_XMUXCTRL_MEMORY_64BIT			0x04 /* >2MB RAM, 512K * 8 & more */
155 #define     TVP3026_XMUXCTRL_PIXEL_4BIT				0x40 /* L0,H0,L1,H1... */
156 #define     TVP3026_XMUXCTRL_PIXEL_4BIT_SWAPPED			0x60 /* H0,L0,H1,L1... */
157 #define     TVP3026_XMUXCTRL_PIXEL_8BIT				0x48
158 #define     TVP3026_XMUXCTRL_PIXEL_16BIT			0x50
159 #define     TVP3026_XMUXCTRL_PIXEL_32BIT			0x58
160 #define     TVP3026_XMUXCTRL_VGA				0x98 /* VGA MEMORY, 8BIT PIXEL */
161 #define TVP3026_XCLKCTRL	0x1A
162 #define     TVP3026_XCLKCTRL_DIV1	0x00
163 #define     TVP3026_XCLKCTRL_DIV2	0x10
164 #define     TVP3026_XCLKCTRL_DIV4	0x20
165 #define     TVP3026_XCLKCTRL_DIV8	0x30
166 #define     TVP3026_XCLKCTRL_DIV16	0x40
167 #define     TVP3026_XCLKCTRL_DIV32	0x50
168 #define     TVP3026_XCLKCTRL_DIV64	0x60
169 #define     TVP3026_XCLKCTRL_CLKSTOPPED	0x70
170 #define     TVP3026_XCLKCTRL_SRC_CLK0	0x00
171 #define     TVP3026_XCLKCTRL_SRC_CLK1   0x01
172 #define     TVP3026_XCLKCTRL_SRC_CLK2	0x02	/* CLK2 is TTL source*/
173 #define     TVP3026_XCLKCTRL_SRC_NCLK2	0x03	/* not CLK2 is TTL source */
174 #define     TVP3026_XCLKCTRL_SRC_ECLK2	0x04	/* CLK2 and not CLK2 is ECL source */
175 #define     TVP3026_XCLKCTRL_SRC_PLL	0x05
176 #define     TVP3026_XCLKCTRL_SRC_DIS	0x06	/* disable & poweroff internal clock */
177 #define     TVP3026_XCLKCTRL_SRC_CLK0VGA 0x07
178 #define TVP3026_XPALETTEPAGE	0x1C
179 #define TVP3026_XGENCTRL	0x1D
180 #define     TVP3026_XGENCTRL_HSYNC_POS	0x00
181 #define     TVP3026_XGENCTRL_HSYNC_NEG	0x01
182 #define     TVP3026_XGENCTRL_VSYNC_POS	0x00
183 #define     TVP3026_XGENCTRL_VSYNC_NEG	0x02
184 #define     TVP3026_XGENCTRL_LITTLE_ENDIAN 0x00
185 #define     TVP3026_XGENCTRL_BIG_ENDIAN    0x08
186 #define     TVP3026_XGENCTRL_BLACK_0IRE		0x00
187 #define     TVP3026_XGENCTRL_BLACK_75IRE	0x10
188 #define     TVP3026_XGENCTRL_NO_SYNC_ON_GREEN	0x00
189 #define     TVP3026_XGENCTRL_SYNC_ON_GREEN	0x20
190 #define     TVP3026_XGENCTRL_OVERSCAN_DIS	0x00
191 #define     TVP3026_XGENCTRL_OVERSCAN_EN	0x40
192 #define TVP3026_XMISCCTRL	0x1E
193 #define     TVP3026_XMISCCTRL_DAC_PUP	0x00
194 #define     TVP3026_XMISCCTRL_DAC_PDOWN	0x01
195 #define     TVP3026_XMISCCTRL_DAC_EXT	0x00 /* or 8, bit 3 is ignored */
196 #define     TVP3026_XMISCCTRL_DAC_6BIT	0x04
197 #define     TVP3026_XMISCCTRL_DAC_8BIT	0x0C
198 #define     TVP3026_XMISCCTRL_PSEL_DIS	0x00
199 #define     TVP3026_XMISCCTRL_PSEL_EN	0x10
200 #define     TVP3026_XMISCCTRL_PSEL_LOW	0x00 /* PSEL high selects directcolor */
201 #define     TVP3026_XMISCCTRL_PSEL_HIGH 0x20 /* PSEL high selects truecolor or pseudocolor */
202 #define TVP3026_XGENIOCTRL	0x2A
203 #define TVP3026_XGENIODATA	0x2B
204 #define TVP3026_XPLLADDR	0x2C
206 #define     TVP3026_XPLLDATA_N		0x00
207 #define     TVP3026_XPLLDATA_M		0x01
208 #define     TVP3026_XPLLDATA_P		0x02
209 #define     TVP3026_XPLLDATA_STAT	0x03
210 #define TVP3026_XPIXPLLDATA	0x2D
211 #define TVP3026_XMEMPLLDATA	0x2E
212 #define TVP3026_XLOOPPLLDATA	0x2F
213 #define TVP3026_XCOLKEYOVRMIN	0x30
214 #define TVP3026_XCOLKEYOVRMAX	0x31
215 #define TVP3026_XCOLKEYREDMIN	0x32
216 #define TVP3026_XCOLKEYREDMAX	0x33
217 #define TVP3026_XCOLKEYGREENMIN	0x34
218 #define TVP3026_XCOLKEYGREENMAX	0x35
219 #define TVP3026_XCOLKEYBLUEMIN	0x36
220 #define TVP3026_XCOLKEYBLUEMAX	0x37
221 #define TVP3026_XCOLKEYCTRL	0x38
222 #define     TVP3026_XCOLKEYCTRL_OVR_EN	0x01
223 #define     TVP3026_XCOLKEYCTRL_RED_EN	0x02
224 #define     TVP3026_XCOLKEYCTRL_GREEN_EN 0x04
225 #define     TVP3026_XCOLKEYCTRL_BLUE_EN	0x08
226 #define     TVP3026_XCOLKEYCTRL_NEGATE	0x10
227 #define     TVP3026_XCOLKEYCTRL_ZOOM1	0x00
228 #define     TVP3026_XCOLKEYCTRL_ZOOM2	0x20
229 #define     TVP3026_XCOLKEYCTRL_ZOOM4	0x40
230 #define     TVP3026_XCOLKEYCTRL_ZOOM8	0x60
231 #define     TVP3026_XCOLKEYCTRL_ZOOM16	0x80
232 #define     TVP3026_XCOLKEYCTRL_ZOOM32	0xA0
233 #define TVP3026_XMEMPLLCTRL	0x39
235 #define     TVP3026_XMEMPLLCTRL_STROBEMKC4	0x08
236 #define     TVP3026_XMEMPLLCTRL_MCLK_DOTCLOCK	0x00	/* MKC4 */
237 #define     TVP3026_XMEMPLLCTRL_MCLK_MCLKPLL	0x10	/* MKC4 */
238 #define     TVP3026_XMEMPLLCTRL_RCLK_PIXPLL	0x00
239 #define     TVP3026_XMEMPLLCTRL_RCLK_LOOPPLL	0x20
240 #define     TVP3026_XMEMPLLCTRL_RCLK_DOTDIVN	0x40	/* dot clock divided by loop pclk N prescaler */
241 #define TVP3026_XSENSETEST	0x3A
242 #define TVP3026_XTESTMODEDATA	0x3B
243 #define TVP3026_XCRCREML	0x3C
244 #define TVP3026_XCRCREMH	0x3D
245 #define TVP3026_XCRCBITSEL	0x3E
246 #define TVP3026_XID		0x3F
261 #define POS3026_XLATCHCTRL	0
272   0x00, TVP3026_XCLKCTRL_DIV1 | TVP3026_XCLKCTRL_SRC_PLL,
273   0x00,
276   0x00,
277   0x1E,
278   0xFF, 0xFF, 0xFF, 0xFF,
279   0xFF, 0xFF, 0xFF, 0xFF,
281   0x00, 0x00, TVP3026_XCURCTRL_DIS };
309 	hw->DACclk[0] = pixin | 0xC0;  in Ti3026_setpclk()
311 	hw->DACclk[2] = pixpost | 0xB0;  in Ti3026_setpclk()
327 		loopdiv = 0; /* div 2 */  in Ti3026_setpclk()
329 			looppost = 0;  in Ti3026_setpclk()
339 			hw->DACclk[3] = ((65 - loopin) & 0x3F) | 0xC0;  in Ti3026_setpclk()
340 			hw->DACclk[4] = (65 - loopfeed) | 0x80;  in Ti3026_setpclk()
341 			if (minfo->accel.ramdac_rev > 0x20) {  in Ti3026_setpclk()
345 					hw->DACclk[4] &= ~0xC0;  in Ti3026_setpclk()
352 					hw->DACclk[4] ^= 0xC0;	/* change from 0x80 to 0x40 */  in Ti3026_setpclk()
356 			hw->DACclk[5] = looppost | 0xF8;  in Ti3026_setpclk()
358 				hw->DACclk[5] ^= 0x40;  in Ti3026_setpclk()
360 			hw->DACclk[3] = ((65 - loopin) & 0x3F) | 0xC0;  in Ti3026_setpclk()
362 			hw->DACclk[5] = looppost | 0xF0;  in Ti3026_setpclk()
366 	return 0;  in Ti3026_setpclk()
412 	hw->MiscOutReg = 0xCB;  in Ti3026_init()
421 	if (minfo->video.len < 0x400000)  in Ti3026_init()
422 		hw->CRTCEXT[3] |= 0x08;  in Ti3026_init()
423 	else if (minfo->video.len > 0x400000)  in Ti3026_init()
424 		hw->CRTCEXT[3] |= 0x10;  in Ti3026_init()
434 	hw->MXoptionReg &= ~0x00001000;  in Ti3026_init()
435 	if (isInterleave(minfo)) hw->MXoptionReg |= 0x00001000;  in Ti3026_init()
439 	return 0;  in Ti3026_init()
455 	outTi3026(minfo, TVP3026_XPLLADDR, 0xFC);  in ti3026_setMCLK()
457 	outTi3026(minfo, TVP3026_XPLLADDR, 0xFD);  in ti3026_setMCLK()
459 	outTi3026(minfo, TVP3026_XPLLADDR, 0xFE);  in ti3026_setMCLK()
463 	outTi3026(minfo, TVP3026_XPLLADDR, 0xFE);  in ti3026_setMCLK()
464 	outTi3026(minfo, TVP3026_XPIXPLLDATA, 0x00);  in ti3026_setMCLK()
467 	outTi3026(minfo, TVP3026_XPLLADDR, 0xFC);  in ti3026_setMCLK()
468 	outTi3026(minfo, TVP3026_XPIXPLLDATA, mclk_n | 0xC0);  in ti3026_setMCLK()
470 	outTi3026(minfo, TVP3026_XPIXPLLDATA, mclk_p | 0xB0);  in ti3026_setMCLK()
474 		if (inTi3026(minfo, TVP3026_XPIXPLLDATA) & 0x40)  in ti3026_setMCLK()
483 	outTi3026(minfo, TVP3026_XMEMPLLCTRL, mclk_ctl & 0xE7);  in ti3026_setMCLK()
484 	outTi3026(minfo, TVP3026_XMEMPLLCTRL, (mclk_ctl & 0xE7) | TVP3026_XMEMPLLCTRL_STROBEMKC4);  in ti3026_setMCLK()
487 	outTi3026(minfo, TVP3026_XPLLADDR, 0xFB);  in ti3026_setMCLK()
488 	outTi3026(minfo, TVP3026_XMEMPLLDATA, 0x00);  in ti3026_setMCLK()
491 	outTi3026(minfo, TVP3026_XPLLADDR, 0xF3);  in ti3026_setMCLK()
492 	outTi3026(minfo, TVP3026_XMEMPLLDATA, mclk_n | 0xC0);  in ti3026_setMCLK()
494 	outTi3026(minfo, TVP3026_XMEMPLLDATA, mclk_p | 0xB0);  in ti3026_setMCLK()
498 		if (inTi3026(minfo, TVP3026_XMEMPLLDATA) & 0x40)  in ti3026_setMCLK()
513 			rfhcnt = 0;  in ti3026_setMCLK()
515 	minfo->hw.MXoptionReg = (minfo->hw.MXoptionReg & ~0x000F0000) | (rfhcnt << 16);  in ti3026_setMCLK()
519 	outTi3026(minfo, TVP3026_XMEMPLLCTRL, (mclk_ctl & 0xE7) | TVP3026_XMEMPLLCTRL_MCLK_MCLKPLL);  in ti3026_setMCLK()
523 	outTi3026(minfo, TVP3026_XPLLADDR, 0xFE);  in ti3026_setMCLK()
524 	outTi3026(minfo, TVP3026_XPIXPLLDATA, 0x00);  in ti3026_setMCLK()
527 	outTi3026(minfo, TVP3026_XPLLADDR, 0xFC);  in ti3026_setMCLK()
534 		if (inTi3026(minfo, TVP3026_XPIXPLLDATA) & 0x40)  in ti3026_setMCLK()
569 	for (i = 0; i < 6; i++)  in Ti3026_restore()
585 	for (i = 0; i < 6; i++)  in Ti3026_restore()
588 	for (i = 0; i < 21; i++) {  in Ti3026_restore()
592 	outTi3026(minfo, TVP3026_XPLLADDR, 0x00);  in Ti3026_restore()
593 	progdac[0] = inTi3026(minfo, TVP3026_XPIXPLLDATA);  in Ti3026_restore()
595 	outTi3026(minfo, TVP3026_XPLLADDR, 0x15);  in Ti3026_restore()
598 	outTi3026(minfo, TVP3026_XPLLADDR, 0x2A);  in Ti3026_restore()
610 		outTi3026(minfo, TVP3026_XPLLADDR, 0x2A);  in Ti3026_restore()
611 		outTi3026(minfo, TVP3026_XLOOPPLLDATA, 0);  in Ti3026_restore()
612 		outTi3026(minfo, TVP3026_XPIXPLLDATA, 0);  in Ti3026_restore()
614 		outTi3026(minfo, TVP3026_XPLLADDR, 0x00);  in Ti3026_restore()
615 		for (i = 0; i < 3; i++)  in Ti3026_restore()
618 		if (hw->MiscOutReg & 0x08) {  in Ti3026_restore()
620 			outTi3026(minfo, TVP3026_XPLLADDR, 0x3F);  in Ti3026_restore()
622 				if (inTi3026(minfo, TVP3026_XPIXPLLDATA) & 0x40)  in Ti3026_restore()
636 		outTi3026(minfo, TVP3026_XPLLADDR, 0x00);  in Ti3026_restore()
640 		if ((hw->MiscOutReg & 0x08) && ((hw->DACclk[5] & 0x80) == 0x80)) {  in Ti3026_restore()
644 			outTi3026(minfo, TVP3026_XPLLADDR, 0x3F);  in Ti3026_restore()
646 				if (inTi3026(minfo, TVP3026_XLOOPPLLDATA) & 0x40)  in Ti3026_restore()
660 	for (i = 0; i < 21; i++) {  in Ti3026_restore()
662 		if ((i & 0x7) == 0x7) dprintk(KERN_DEBUG "continuing... ");  in Ti3026_restore()
665 	for (i = 0; i < 6; i++)  in Ti3026_restore()
686 					  2048, 0};  in Ti3026_preinit()
689 					  2048, 0};  in Ti3026_preinit()
700 	minfo->outputs[0].data = minfo;  in Ti3026_preinit()
701 	minfo->outputs[0].output = &ti3026_output;  in Ti3026_preinit()
702 	minfo->outputs[0].src = minfo->outputs[0].default_src;  in Ti3026_preinit()
703 	minfo->outputs[0].mode = MATROXFB_OUTPUT_MODE_MONITOR;  in Ti3026_preinit()
706 		return 0;  in Ti3026_preinit()
708 	hw->MXoptionReg &= 0xC0000100;  in Ti3026_preinit()
709 	hw->MXoptionReg |= 0x002C0000;  in Ti3026_preinit()
711 		hw->MXoptionReg &= ~0x00000100;  in Ti3026_preinit()
713 		hw->MXoptionReg &= ~0x40000000;  in Ti3026_preinit()
715 		hw->MXoptionReg |=  0x20000000;  in Ti3026_preinit()
724 	outTi3026(minfo, TVP3026_XPLLADDR, 0x2A);  in Ti3026_preinit()
725 	outTi3026(minfo, TVP3026_XLOOPPLLDATA, 0x00);  in Ti3026_preinit()
726 	outTi3026(minfo, TVP3026_XPIXPLLDATA, 0x00);  in Ti3026_preinit()
728 	mga_outb(M_MISC_REG, 0x67);  in Ti3026_preinit()
734 	mga_outl(M_RESET, 0);  in Ti3026_preinit()
736 	mga_outl(M_MACCESS, 0x00008000);  in Ti3026_preinit()
738 	return 0;  in Ti3026_preinit()