Lines Matching +full:vco +full:- +full:hz
69 #define STG4K3_PLL_MIN_VCO_SC (100000000 >> STG4K3_PLL_SCALER) /* Min VCO rate */
70 #define STG4K3_PLL_MAX_VCO_SC (500000000 >> STG4K3_PLL_SCALER) /* Max VCO rate */
71 #define STG4K3_PLL_MINR_VCO_SC (100000000 >> STG4K3_PLL_SCALER) /* Min VCO rate (restricted) */
72 #define STG4K3_PLL_MAXR_VCO_SC (500000000 >> STG4K3_PLL_SCALER) /* Max VCO rate (restricted) */
73 #define STG4K3_PLL_MINR_VCO 100000000 /* Min VCO rate (restricted) */
74 #define STG4K3_PLL_MAX_VCO 500000000 /* Max VCO rate */
75 #define STG4K3_PLL_MAXR_VCO 500000000 /* Max VCO rate (restricted) */
101 /* Program SD-RAM interface */ in InitSDRAMRegisters()
129 /* Translate clock in Hz */ in ProgramClock()
130 coreClock *= 100; /* in Hz */ in ProgramClock()
131 refClock *= 1000; /* in Hz */ in ProgramClock()
134 * The method calculates ~ +- 0.4% (1/256) in ProgramClock()
136 ulMinClock = coreClock - (coreClock >> 8); in ProgramClock()
147 /* loop for pre-divider from min to max */ in ProgramClock()
157 F--; in ProgramClock()
167 /* Calc VCO at full accuracy */ in ProgramClock()
172 * Check it's within restricted VCO range in ProgramClock()
175 * against VCO limit in ProgramClock()
181 ulTmp = (ulVCO >> OD); /* Clock = VCO / (2^OD) */ in ProgramClock()
186 …ulPhaseScore = (((refClock / R) - (refClock / STG4K3_PLL_MAX_R))) / ((refClock - (refClock / STG4K… in ProgramClock()
188 …ulVcoScore = ((ulVCO - STG4K3_PLL_MINR_VCO)) / ((STG4K3_PLL_MAXR_VCO - STG4K3_PLL_MINR_VCO) >> 10); in ProgramClock()
200 /*-------------------------------------------------------------------------- in ProgramClock()
202 value at the phase comparater and the VCO output in ProgramClock()
206 … --------------------------------------------------------------------------*/ in ProgramClock()
277 (u32)pDev->revision); in SetCoreClockPLL()
280 return -EINVAL; in SetCoreClockPLL()
284 core_pll |= ((P) | ((F - 2) << 2) | ((R - 2) << 11)); in SetCoreClockPLL()
292 not reliably set when the code is compiled -O3 in SetCoreClockPLL()