video/fbdev/cyber2000fb.h

1 /* SPDX-License-Identifier: GPL-2.0-only */
5  *  Copyright (C) 1998-2000 Russell King
80 #define PCI_BM_CTL_ENABLE		0x01	/* enable bus-master			*/
246 #define EXT_MEM_START		0xc0		/* ext start address 21 bits		*/
248 #define EXT_SRC_WIDTH		0xc3		/* ext offset phase  10 bits		*/
250 #define EXT_X_START		0xc5		/* ext->screen, 16 bits			*/
251 #define EXT_X_END		0xc7		/* ext->screen, 16 bits			*/
252 #define EXT_Y_START		0xc9		/* ext->screen, 16 bits			*/
253 #define EXT_Y_END		0xcb		/* ext->screen, 16 bits			*/
256 #define EXT_DDA_X_INIT		0xd1		/* ext->screen 16 bits			*/
257 #define EXT_DDA_X_INC		0xd3		/* ext->screen 16 bits			*/
258 #define EXT_DDA_Y_INIT		0xd5		/* ext->screen 16 bits			*/
259 #define EXT_DDA_Y_INC		0xd7		/* ext->screen 16 bits			*/
264 #define EXT_VID_FMT_YUV422		0x00	/* formats - does this cause conversion? */
308 #define VFAC_CTL2_INVERT_VIDDATAVALID	0x01	/* invert video data valid		*/
309 #define VFAC_CTL2_INVERT_GRAPHREADY	0x02	/* invert graphic ready output sig	*/
310 #define VFAC_CTL2_INVERT_DATACLK	0x04	/* invert data clock signal		*/
311 #define VFAC_CTL2_INVERT_HSYNC		0x08	/* invert hsync input			*/
312 #define VFAC_CTL2_INVERT_VSYNC		0x10	/* invert vsync input			*/
313 #define VFAC_CTL2_INVERT_FRAME		0x20	/* invert frame odd/even input		*/
314 #define VFAC_CTL2_INVERT_BLANK		0x40	/* invert blank output			*/
315 #define VFAC_CTL2_INVERT_OVSYNC		0x80	/* invert other vsync input		*/
349  * Bus-master
360 #define BM_COUNT		0xbc090		/* read-only				*/
397 #define TV_CTL			0xbe4dc	/* reflects a previous register- MVFCLR, MVPCLR etc P241*/
405  * Graphics Co-processor