Lines Matching +full:0 +full:x600000
63 #define in_8(addr) 0
65 #define in_le32(addr) 0
100 for (i = 0; i < 3; i++) in PAR_EQUAL()
103 return 0; in PAR_EQUAL()
104 for (i = 0; i < 16; i++) in PAR_EQUAL()
107 return 0; in PAR_EQUAL()
179 return 0; in controlfb_setcolreg()
193 for (i = 0; i < 3; ++i) { in set_control_clock()
195 0x50, i + 1, params[i]); in set_control_clock()
245 out_le32(CNTRL_REG(p,ctrl), 0x400 | par->ctrl); in control_set_hardware()
249 RADACAL_WRITE(0x20, r->radacal_ctrl); in control_set_hardware()
250 RADACAL_WRITE(0x21, p->control_use_bank2 ? 0 : 1); in control_set_hardware()
251 RADACAL_WRITE(0x10, 0); in control_set_hardware()
252 RADACAL_WRITE(0x11, 0); in control_set_hardware()
255 for (i = 0; i < 16; ++i, ++rp) in control_set_hardware()
263 out_le32(CNTRL_REG(p,rfrcnt), 0x1e5); in control_set_hardware()
264 out_le32(CNTRL_REG(p,intr_ena), 0); in control_set_hardware()
286 * VRAM Bank 2 will be accessible through offset 0x600000 if present in find_vram_size()
289 out_le32(CNTRL_REG(p,vram_attr), 0x31); in find_vram_size()
291 out_8(&p->frame_buffer[0x600000], 0xb3); in find_vram_size()
292 out_8(&p->frame_buffer[0x600001], 0x71); in find_vram_size()
293 invalid_vram_cache(&p->frame_buffer[0x600000]); in find_vram_size()
295 bank2 = (in_8(&p->frame_buffer[0x600000]) == 0xb3) in find_vram_size()
296 && (in_8(&p->frame_buffer[0x600001]) == 0x71); in find_vram_size()
300 * VRAM Bank 1 will be accessible through offset 0x000000 if present in find_vram_size()
303 out_le32(CNTRL_REG(p,vram_attr), 0x39); in find_vram_size()
305 out_8(&p->frame_buffer[0], 0x5a); in find_vram_size()
306 out_8(&p->frame_buffer[1], 0xc7); in find_vram_size()
307 invalid_vram_cache(&p->frame_buffer[0]); in find_vram_size()
309 bank1 = (in_8(&p->frame_buffer[0]) == 0x5a) in find_vram_size()
310 && (in_8(&p->frame_buffer[1]) == 0xc7); in find_vram_size()
318 p->vram_attr = 0x39; in find_vram_size()
319 p->frame_buffer += 0x600000; in find_vram_size()
320 p->frame_buffer_phys += 0x600000; in find_vram_size()
325 p->vram_attr = 0x51; in find_vram_size()
331 p->vram_attr = 0x31; in find_vram_size()
334 p->total_vram = (bank1 + bank2) * 0x200000; in find_vram_size()
354 sense = (in_le32(CNTRL_REG(p,mon_sense)) & 0x1c0) << 2; in read_control_sense()
359 sense |= (in_le32(CNTRL_REG(p,mon_sense)) & 0xc0) >> 2; in read_control_sense()
362 sense |= ((in_le32(CNTRL_REG(p,mon_sense)) & 0x100) >> 5) in read_control_sense()
363 | ((in_le32(CNTRL_REG(p,mon_sense)) & 0x40) >> 4); in read_control_sense()
366 sense |= (in_le32(CNTRL_REG(p,mon_sense)) & 0x180) >> 7; in read_control_sense()
391 p0 = 0; in calc_clock_params()
392 p1 = 0; in calc_clock_params()
408 param[0] = p0; in calc_clock_params()
412 return 0; in calc_clock_params()
435 if (p->total_vram > 0x200000) { in control_var_to_par()
437 r->radacal_ctrl = 0x20; in control_var_to_par()
441 r->radacal_ctrl = 0x10; in control_var_to_par()
448 if (p->total_vram > 0x200000) { in control_var_to_par()
450 r->radacal_ctrl = 0x24; in control_var_to_par()
454 r->radacal_ctrl = 0x14; in control_var_to_par()
460 if (p->total_vram > 0x200000) { in control_var_to_par()
462 r->radacal_ctrl = 0x28; in control_var_to_par()
464 r->mode = 0; in control_var_to_par()
465 r->radacal_ctrl = 0x18; in control_var_to_par()
525 r->regs[0] = vswin; in control_var_to_par()
543 par->ctrl = 0x7f; in control_var_to_par()
545 par->ctrl = 0x3b; in control_var_to_par()
548 par->vmode = 0; in control_var_to_par()
550 return 0; in control_var_to_par()
564 memset(var, 0, sizeof(*var)); in control_par_to_var()
614 * 10^12 * clock_params[0] / (3906400 * clock_params[1] in control_par_to_var()
616 * (10^12 * clock_params[0] / (3906400 * clock_params[1])) in control_par_to_var()
619 /* (255990.17 * clock_params[0] / clock_params[1]) >> clock_params[2] */ in control_par_to_var()
620 var->pixclock = CONTROL_PIXCLOCK_BASE * par->regvals.clock_params[0]; in control_par_to_var()
640 return 0; in controlfb_check_var()
667 return 0; in controlfb_set_par()
681 hstep = 0x1f >> par->cmode; in controlfb_pan_display()
690 return 0; in controlfb_pan_display()
700 if (blank_mode > 0) in controlfb_blank()
706 ctrl &= ~0x30; in controlfb_blank()
709 ctrl &= ~0x33; in controlfb_blank()
712 ctrl |= 0x400; in controlfb_blank()
718 ctrl &= ~0x400; in controlfb_blank()
719 ctrl |= 0x33; in controlfb_blank()
723 return 0; in controlfb_blank()
780 fb_alloc_cmap(&info->cmap, 256, 0); in control_init_info()
789 info->fix.ywrapstep = 0; in control_init_info()
790 info->fix.type_aux = 0; in control_init_info()
806 int vmode = simple_strtoul(this_opt+6, NULL, 0); in control_setup()
807 if (vmode > 0 && vmode <= VMODE_MAX && in control_setup()
808 control_mac_modes[vmode - 1].m[1] >= 0) in control_setup()
811 int depth = simple_strtoul(this_opt+6, NULL, 0); in control_setup()
845 full = p->total_vram == 0x400000; in init_control()
860 printk(KERN_CONT "Monitor sense value = 0x%x, ", sense); in init_control()
862 if (control_mac_modes[vmode - 1].m[full] < 0) in init_control()
871 if (mac_vmode_to_var(vmode, cmode, &var) < 0) { in init_control()
877 if (mac_vmode_to_var(vmode, cmode, &var) < 0) { in init_control()
896 if (register_framebuffer(&p->info) < 0) in init_control()
901 return 0; in init_control()
917 p->frame_buffer -= 0x600000; in control_cleanup()
921 release_mem_region(p->cmap_regs_phys, 0x1000); in control_cleanup()
956 p->frame_buffer_phys = fb_res.start + 0x800000; in control_of_init()
962 p->fb_orig_base = 0; in control_of_init()
966 p->frame_buffer = ioremap_wt(p->frame_buffer_phys, 0x800000); in control_of_init()
971 p->control_regs_phys = 0; in control_of_init()
976 p->cmap_regs_phys = 0xf301b000; /* XXX not in prom? */ in control_of_init()
977 if (!request_mem_region(p->cmap_regs_phys, 0x1000, "controlfb cmap")) { in control_of_init()
978 p->cmap_regs_phys = 0; in control_of_init()
981 p->cmap_regs = ioremap(p->cmap_regs_phys, 0x1000); in control_of_init()
990 if (init_control(p) < 0) in control_of_init()
993 return 0; in control_of_init()
1012 ret = 0; in control_init()