Lines Matching refs:INREG
338 if ((INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK) > CFG_ATI_REV_A13) in radeon_pm_enable_dynamic_mode()
421 if (INREG(MEM_CNTL) & R300_MEM_USE_CD_CH_ONLY) in radeon_pm_enable_dynamic_mode()
473 ((INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK) < CFG_ATI_REV_A13)) || in radeon_pm_enable_dynamic_mode()
475 ((INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK) <= CFG_ATI_REV_A13))) { in radeon_pm_enable_dynamic_mode()
491 ((INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK) < CFG_ATI_REV_A13)) in radeon_pm_enable_dynamic_mode()
502 ((INREG(CNFG_CNTL) & CFG_ATI_REV_ID_MASK) < CFG_ATI_REV_A13)) { in radeon_pm_enable_dynamic_mode()
558 return INREG( MC_IND_DATA); in INMC()
573 rinfo->save_regs[9] = INREG(DISP_MISC_CNTL); in radeon_pm_save_regs()
574 rinfo->save_regs[10] = INREG(DISP_PWR_MAN); in radeon_pm_save_regs()
575 rinfo->save_regs[11] = INREG(LVDS_GEN_CNTL); in radeon_pm_save_regs()
576 rinfo->save_regs[13] = INREG(TV_DAC_CNTL); in radeon_pm_save_regs()
577 rinfo->save_regs[14] = INREG(BUS_CNTL1); in radeon_pm_save_regs()
578 rinfo->save_regs[15] = INREG(CRTC_OFFSET_CNTL); in radeon_pm_save_regs()
579 rinfo->save_regs[16] = INREG(AGP_CNTL); in radeon_pm_save_regs()
580 rinfo->save_regs[17] = (INREG(CRTC_GEN_CNTL) & 0xfdffffff) | 0x04000000; in radeon_pm_save_regs()
581 rinfo->save_regs[18] = (INREG(CRTC2_GEN_CNTL) & 0xfdffffff) | 0x04000000; in radeon_pm_save_regs()
582 rinfo->save_regs[19] = INREG(GPIOPAD_A); in radeon_pm_save_regs()
583 rinfo->save_regs[20] = INREG(GPIOPAD_EN); in radeon_pm_save_regs()
584 rinfo->save_regs[21] = INREG(GPIOPAD_MASK); in radeon_pm_save_regs()
585 rinfo->save_regs[22] = INREG(ZV_LCDPAD_A); in radeon_pm_save_regs()
586 rinfo->save_regs[23] = INREG(ZV_LCDPAD_EN); in radeon_pm_save_regs()
587 rinfo->save_regs[24] = INREG(ZV_LCDPAD_MASK); in radeon_pm_save_regs()
588 rinfo->save_regs[25] = INREG(GPIO_VGA_DDC); in radeon_pm_save_regs()
589 rinfo->save_regs[26] = INREG(GPIO_DVI_DDC); in radeon_pm_save_regs()
590 rinfo->save_regs[27] = INREG(GPIO_MONID); in radeon_pm_save_regs()
591 rinfo->save_regs[28] = INREG(GPIO_CRT2_DDC); in radeon_pm_save_regs()
593 rinfo->save_regs[29] = INREG(SURFACE_CNTL); in radeon_pm_save_regs()
594 rinfo->save_regs[30] = INREG(MC_FB_LOCATION); in radeon_pm_save_regs()
595 rinfo->save_regs[31] = INREG(DISPLAY_BASE_ADDR); in radeon_pm_save_regs()
596 rinfo->save_regs[32] = INREG(MC_AGP_LOCATION); in radeon_pm_save_regs()
597 rinfo->save_regs[33] = INREG(CRTC2_DISPLAY_BASE_ADDR); in radeon_pm_save_regs()
600 rinfo->save_regs[35] = INREG(MEM_SDRAM_MODE_REG); in radeon_pm_save_regs()
601 rinfo->save_regs[36] = INREG(BUS_CNTL); in radeon_pm_save_regs()
602 rinfo->save_regs[39] = INREG(RBBM_CNTL); in radeon_pm_save_regs()
603 rinfo->save_regs[40] = INREG(DAC_CNTL); in radeon_pm_save_regs()
604 rinfo->save_regs[41] = INREG(HOST_PATH_CNTL); in radeon_pm_save_regs()
605 rinfo->save_regs[37] = INREG(MPP_TB_CONFIG); in radeon_pm_save_regs()
606 rinfo->save_regs[38] = INREG(FCP_CNTL); in radeon_pm_save_regs()
609 rinfo->save_regs[12] = INREG(LVDS_PLL_CNTL); in radeon_pm_save_regs()
615 rinfo->save_regs[81] = INREG(LVDS_GEN_CNTL); in radeon_pm_save_regs()
619 rinfo->save_regs[42] = INREG(MEM_REFRESH_CNTL); in radeon_pm_save_regs()
620 rinfo->save_regs[46] = INREG(MC_CNTL); in radeon_pm_save_regs()
621 rinfo->save_regs[47] = INREG(MC_INIT_GFX_LAT_TIMER); in radeon_pm_save_regs()
622 rinfo->save_regs[48] = INREG(MC_INIT_MISC_LAT_TIMER); in radeon_pm_save_regs()
623 rinfo->save_regs[49] = INREG(MC_TIMING_CNTL); in radeon_pm_save_regs()
624 rinfo->save_regs[50] = INREG(MC_READ_CNTL_AB); in radeon_pm_save_regs()
625 rinfo->save_regs[51] = INREG(MC_IOPAD_CNTL); in radeon_pm_save_regs()
626 rinfo->save_regs[52] = INREG(MC_CHIP_IO_OE_CNTL_AB); in radeon_pm_save_regs()
627 rinfo->save_regs[53] = INREG(MC_DEBUG); in radeon_pm_save_regs()
629 rinfo->save_regs[54] = INREG(PAMAC0_DLY_CNTL); in radeon_pm_save_regs()
630 rinfo->save_regs[55] = INREG(PAMAC1_DLY_CNTL); in radeon_pm_save_regs()
631 rinfo->save_regs[56] = INREG(PAD_CTLR_MISC); in radeon_pm_save_regs()
632 rinfo->save_regs[57] = INREG(FW_CNTL); in radeon_pm_save_regs()
666 rinfo->save_regs[79] = INREG(PAMAC2_DLY_CNTL); in radeon_pm_save_regs()
668 rinfo->save_regs[80] = INREG(OV0_BASE_ADDR); in radeon_pm_save_regs()
669 rinfo->save_regs[82] = INREG(FP_GEN_CNTL); in radeon_pm_save_regs()
670 rinfo->save_regs[83] = INREG(FP2_GEN_CNTL); in radeon_pm_save_regs()
671 rinfo->save_regs[84] = INREG(TMDS_CNTL); in radeon_pm_save_regs()
672 rinfo->save_regs[85] = INREG(TMDS_TRANSMITTER_CNTL); in radeon_pm_save_regs()
673 rinfo->save_regs[86] = INREG(DISP_OUTPUT_CNTL); in radeon_pm_save_regs()
674 rinfo->save_regs[87] = INREG(DISP_HW_DEBUG); in radeon_pm_save_regs()
675 rinfo->save_regs[88] = INREG(TV_MASTER_CNTL); in radeon_pm_save_regs()
679 rinfo->save_regs[94] = INREG(GRPH_BUFFER_CNTL); in radeon_pm_save_regs()
680 rinfo->save_regs[95] = INREG(GRPH2_BUFFER_CNTL); in radeon_pm_save_regs()
681 rinfo->save_regs[96] = INREG(HDP_DEBUG); in radeon_pm_save_regs()
781 reg = INREG(BUS_CNTL1); in radeon_pm_low_current()
797 reg = INREG(TV_DAC_CNTL); in radeon_pm_low_current()
804 reg = INREG(TMDS_TRANSMITTER_CNTL); in radeon_pm_low_current()
808 reg = INREG(DAC_CNTL); in radeon_pm_low_current()
812 reg = INREG(DAC_CNTL2); in radeon_pm_low_current()
816 reg = INREG(TV_DAC_CNTL); in radeon_pm_low_current()
910 OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) & in radeon_pm_setup_for_suspend()
963 OUTREG(BUS_CNTL1, INREG(BUS_CNTL1) | BUS_CNTL1__AGPCLK_VALID); in radeon_pm_setup_for_suspend()
965 (INREG(BUS_CNTL1) & ~BUS_CNTL1__MOBILE_PLATFORM_SEL_MASK) in radeon_pm_setup_for_suspend()
968 OUTREG(BUS_CNTL1, INREG(BUS_CNTL1)); in radeon_pm_setup_for_suspend()
969 OUTREG(BUS_CNTL1, (INREG(BUS_CNTL1) & ~0x4000) | 0x8000); in radeon_pm_setup_for_suspend()
974 OUTREG(CRTC_OFFSET_CNTL, (INREG(CRTC_OFFSET_CNTL) in radeon_pm_setup_for_suspend()
983 (INREG(AGP_CNTL) & ~(AGP_CNTL__MAX_IDLE_CLK_MASK)) in radeon_pm_setup_for_suspend()
992 disp_mis_cntl = INREG(DISP_MISC_CNTL); in radeon_pm_setup_for_suspend()
1009 disp_pwr_man = INREG(DISP_PWR_MAN); in radeon_pm_setup_for_suspend()
1034 disp_pwr_man = INREG(DISP_PWR_MAN); in radeon_pm_setup_for_suspend()
1050 OUTREG( CRTC_GEN_CNTL, (INREG( CRTC_GEN_CNTL) & ~CRTC_GEN_CNTL__CRTC_EN) in radeon_pm_setup_for_suspend()
1052 OUTREG( CRTC2_GEN_CNTL, (INREG( CRTC2_GEN_CNTL) & ~CRTC2_GEN_CNTL__CRTC2_EN) in radeon_pm_setup_for_suspend()
1104 mem_sdram_mode = INREG( MEM_SDRAM_MODE_REG); in radeon_pm_program_mode_reg()
1127 } while ((INREG(MC_STATUS) in radeon_pm_program_mode_reg()
1139 if (INREG(MC_STATUS) & (MC_STATUS__MEM_PWRUP_COMPL_A in radeon_pm_m10_program_mode_wait()
1204 mc = INREG(MC_CNTL); in radeon_pm_enable_dll_m10()
1252 crtcGenCntl = INREG( CRTC_GEN_CNTL); in radeon_pm_full_reset_sdram()
1253 crtcGenCntl2 = INREG( CRTC2_GEN_CNTL); in radeon_pm_full_reset_sdram()
1255 crtc_more_cntl = INREG( CRTC_MORE_CNTL); in radeon_pm_full_reset_sdram()
1256 fp_gen_cntl = INREG( FP_GEN_CNTL); in radeon_pm_full_reset_sdram()
1257 fp2_gen_cntl = INREG( FP2_GEN_CNTL); in radeon_pm_full_reset_sdram()
1285 memRefreshCntl = INREG( MEM_REFRESH_CNTL) in radeon_pm_full_reset_sdram()
1331 memRefreshCntl = INREG( MEM_REFRESH_CNTL) in radeon_pm_full_reset_sdram()
1339 INREG( MEM_SDRAM_MODE_REG) & ~MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE); in radeon_pm_full_reset_sdram()
1346 INREG(MEM_SDRAM_MODE_REG) | MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE); in radeon_pm_full_reset_sdram()
1354 memRefreshCntl = INREG(EXT_MEM_CNTL) & ~(1 << 20); in radeon_pm_full_reset_sdram()
1359 INREG( MEM_SDRAM_MODE_REG) in radeon_pm_full_reset_sdram()
1377 INREG( MEM_SDRAM_MODE_REG) | MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE); in radeon_pm_full_reset_sdram()
1385 memRefreshCntl = INREG( MEM_REFRESH_CNTL) in radeon_pm_full_reset_sdram()
1392 INREG( MEM_SDRAM_MODE_REG) in radeon_pm_full_reset_sdram()
1418 INREG( MEM_SDRAM_MODE_REG) | MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE); in radeon_pm_full_reset_sdram()
1440 INREG(PAD_CTLR_STRENGTH); in radeon_pm_reset_pad_ctlr_strength()
1441 OUTREG(PAD_CTLR_STRENGTH, INREG(PAD_CTLR_STRENGTH) & ~PAD_MANUAL_OVERRIDE); in radeon_pm_reset_pad_ctlr_strength()
1442 tmp = INREG(PAD_CTLR_STRENGTH); in radeon_pm_reset_pad_ctlr_strength()
1445 tmp2 = INREG(PAD_CTLR_STRENGTH); in radeon_pm_reset_pad_ctlr_strength()
1561 r2ec = INREG(VGA_DDA_ON_OFF); in radeon_pm_m10_disable_spread_spectrum()
1588 r2ec = INREG(VGA_DDA_ON_OFF); in radeon_pm_m10_enable_lvds_spread_spectrum()
1612 tmp = INREG(LVDS_GEN_CNTL); in radeon_pm_m10_enable_lvds_spread_spectrum()
1616 tmp = INREG(LVDS_PLL_CNTL); in radeon_pm_m10_enable_lvds_spread_spectrum()
1625 INREG(RBBM_STATUS); in radeon_pm_m10_enable_lvds_spread_spectrum()
1739 OUTREG(DAC_MACRO_CNTL, (INREG(DAC_MACRO_CNTL) & ~0x6) | 8); in radeon_reinitialize_M10()
1740 OUTREG(DAC_MACRO_CNTL, (INREG(DAC_MACRO_CNTL) & ~0x6) | 8); in radeon_reinitialize_M10()
1743 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | DAC2_EXPAND_MODE); in radeon_reinitialize_M10()
1755 INREG(SURFACE_CNTL); in radeon_reinitialize_M10()
1761 tmp = INREG(TV_DAC_CNTL) & ~TV_DAC_CNTL_BGADJ_MASK; in radeon_reinitialize_M10()
1765 tmp = INREG(TV_DAC_CNTL) & ~TV_DAC_CNTL_DACADJ_MASK; in radeon_reinitialize_M10()
1791 OUTREG(CRTC_GEN_CNTL, INREG(CRTC_GEN_CNTL) in radeon_reinitialize_M10()
1793 OUTREG(CRTC2_GEN_CNTL, INREG(CRTC2_GEN_CNTL) in radeon_reinitialize_M10()
1798 OUTREG(MEM_REFRESH_CNTL, INREG(MEM_REFRESH_CNTL) in radeon_reinitialize_M10()
1897 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | 0x20); in radeon_reinitialize_M10()
1900 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) & ~20); in radeon_reinitialize_M10()
1905 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) & ~0x20); in radeon_reinitialize_M10()
1929 OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) | LVDS_DIGON | LVDS_ON); in radeon_reinitialize_M10()
1994 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | DAC2_EXPAND_MODE); in radeon_reinitialize_M9P()
2006 INREG(SURFACE_CNTL); in radeon_reinitialize_M9P()
2012 tmp = INREG(TV_DAC_CNTL) & ~TV_DAC_CNTL_BGADJ_MASK; in radeon_reinitialize_M9P()
2016 tmp = INREG(TV_DAC_CNTL) & ~TV_DAC_CNTL_DACADJ_MASK; in radeon_reinitialize_M9P()
2038 OUTREG(MEM_REFRESH_CNTL, INREG(MEM_REFRESH_CNTL) in radeon_reinitialize_M9P()
2129 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | 0x20); in radeon_reinitialize_M9P()
2132 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) & ~20); in radeon_reinitialize_M9P()
2137 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) & ~0x20); in radeon_reinitialize_M9P()
2168 OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) | LVDS_BLON); in radeon_reinitialize_M9P()
2198 OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) | LVDS_DIGON | LVDS_ON); in radeon_reinitialize_M9P()
2227 INREG(PAD_CTLR_STRENGTH);
2228 OUTREG(PAD_CTLR_STRENGTH, INREG(PAD_CTLR_STRENGTH) & ~0x10000);
2231 INREG(PAD_CTLR_STRENGTH);
2234 OUTREG(DISP_TEST_DEBUG_CNTL, INREG(DISP_TEST_DEBUG_CNTL) | 0x10000000);
2235 OUTREG(OV0_FLAG_CNTRL, INREG(OV0_FLAG_CNTRL) | 0x100);
2236 OUTREG(CRTC_GEN_CNTL, INREG(CRTC_GEN_CNTL));
2238 OUTREG(CRTC2_GEN_CNTL, INREG(CRTC2_GEN_CNTL));
2239 OUTREG(DAC_CNTL2, INREG(DAC_CNTL2) | 0x4000);
2251 OUTREG(CRTC_MORE_CNTL, INREG(CRTC_MORE_CNTL));
2376 INREG(FP_GEN_CNTL);
2378 tmp = INREG(FP_GEN_CNTL);
2382 tmp = INREG(DISP_OUTPUT_CNTL);
2410 tmp = INREG(FP_GEN_CNTL);
2411 tmp2 = INREG(TMDS_TRANSMITTER_CNTL);
2421 tmp = INREG(CRTC_MORE_CNTL);
2424 cgc = INREG(CRTC_GEN_CNTL);
2425 cec = INREG(CRTC_EXT_CNTL);
2426 c2gc = INREG(CRTC2_GEN_CNTL);
2459 tmp = INREG(CLOCK_CNTL_INDEX);
2493 tmp2 = INREG(FP_GEN_CNTL);
2494 tmp = INREG(TMDS_TRANSMITTER_CNTL);
2509 cgc = INREG(CRTC_GEN_CNTL);
2680 OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) & ~(LVDS_BL_MOD_EN)); in radeonfb_pci_suspend_late()
2682 OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) & ~(LVDS_EN | LVDS_ON)); in radeonfb_pci_suspend_late()
2683 OUTREG(LVDS_PLL_CNTL, (INREG(LVDS_PLL_CNTL) & ~30000) | 0x20000); in radeonfb_pci_suspend_late()
2685 OUTREG(LVDS_GEN_CNTL, INREG(LVDS_GEN_CNTL) & ~(LVDS_DIGON)); in radeonfb_pci_suspend_late()
2902 OUTREG(TV_DAC_CNTL, INREG(TV_DAC_CNTL) | 0x07000000); in radeonfb_pm_init()