306 		OUTREG(CLOCK_CNTL_INDEX, tmp);  in radeon_pll_errata_after_data_slow()
308 		OUTREG(CLOCK_CNTL_INDEX, save);  in radeon_pll_errata_after_data_slow()
321 	OUTREG(addr, tmp);  in _OUTREGP()
340 	OUTREG(CLOCK_CNTL_DATA, val);  in __OUTPLL()
432 	OUTREG(MPP_TB_CONFIG, temp);  in radeon_map_ROM()
960 	OUTREG(CRTC_OFFSET, (var->yoffset * info->fix.line_length +  in radeonfb_pan_display()
1000 			OUTREG(LVDS_GEN_CNTL, tmp);  in radeonfb_ioctl()
1014 			OUTREG(CRTC_EXT_CNTL, tmp);  in radeonfb_ioctl()
1070 	OUTREG(CRTC_EXT_CNTL, val);  in radeon_screen_blank()
1092 				OUTREG(LVDS_GEN_CNTL, target_val);  in radeon_screen_blank()
1094 				OUTREG(LVDS_GEN_CNTL, target_val  in radeon_screen_blank()
1101 					OUTREG(LVDS_GEN_CNTL, target_val);  in radeon_screen_blank()
1112 			OUTREG(LVDS_GEN_CNTL, val);  in radeon_screen_blank()
1125 			OUTREG(LVDS_GEN_CNTL, val);  in radeon_screen_blank()
1128 			OUTREG(LVDS_GEN_CNTL, val);  in radeon_screen_blank()
1195 		                OUTREG(PALETTE_INDEX, pindex>>1);  in radeon_setcolreg()
1196 	       	         	OUTREG(PALETTE_DATA,  in radeon_setcolreg()
1205 			OUTREG(PALETTE_INDEX, pindex);  in radeon_setcolreg()
1206 			OUTREG(PALETTE_DATA, (red << 16) |  in radeon_setcolreg()
1250 			OUTREG(DAC_CNTL2, dac_cntl2);  in radeonfb_setcolreg()
1280 			OUTREG(DAC_CNTL2, dac_cntl2);  in radeonfb_setcmap()
1450 	OUTREG(LVDS_GEN_CNTL, rinfo->pending_lvds_gen_cntl);  in radeon_lvds_timer_func()
1471 		OUTREG(common_regs[i].reg, common_regs[i].val);  in radeon_write_mode()
1475 		OUTREG(SURFACE0_LOWER_BOUND + 0x10*i, mode->surf_lower_bound[i]);  in radeon_write_mode()
1476 		OUTREG(SURFACE0_UPPER_BOUND + 0x10*i, mode->surf_upper_bound[i]);  in radeon_write_mode()
1477 		OUTREG(SURFACE0_INFO + 0x10*i, mode->surf_info[i]);  in radeon_write_mode()
1480 	OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl);  in radeon_write_mode()
1483 	OUTREG(CRTC_MORE_CNTL, mode->crtc_more_cntl);  in radeon_write_mode()
1485 	OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp);  in radeon_write_mode()
1486 	OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid);  in radeon_write_mode()
1487 	OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp);  in radeon_write_mode()
1488 	OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid);  in radeon_write_mode()
1489 	OUTREG(CRTC_OFFSET, 0);  in radeon_write_mode()
1490 	OUTREG(CRTC_OFFSET_CNTL, 0);  in radeon_write_mode()
1491 	OUTREG(CRTC_PITCH, mode->crtc_pitch);  in radeon_write_mode()
1492 	OUTREG(SURFACE_CNTL, mode->surface_cntl);  in radeon_write_mode()
1498 		OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp);  in radeon_write_mode()
1499 		OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp);  in radeon_write_mode()
1500 		OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid);  in radeon_write_mode()
1501 		OUTREG(FP_V_SYNC_STRT_WID, mode->fp_v_sync_strt_wid);  in radeon_write_mode()
1502 		OUTREG(FP_HORZ_STRETCH, mode->fp_horz_stretch);  in radeon_write_mode()
1503 		OUTREG(FP_VERT_STRETCH, mode->fp_vert_stretch);  in radeon_write_mode()
1504 		OUTREG(FP_GEN_CNTL, mode->fp_gen_cntl);  in radeon_write_mode()
1505 		OUTREG(TMDS_CRC, mode->tmds_crc);  in radeon_write_mode()
1506 		OUTREG(TMDS_TRANSMITTER_CNTL, mode->tmds_transmitter_cntl);  in radeon_write_mode()
2029 		OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl | CRTC2_DISP_REQ_EN_B);  in fixup_memory_mappings()
2034 	OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl | CRTC_DISPLAY_DIS);  in fixup_memory_mappings()
2035 	OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl | CRTC_DISP_REQ_EN_B);  in fixup_memory_mappings()
2043 	OUTREG(MC_FB_LOCATION,  in fixup_memory_mappings()
2047 	OUTREG(MC_FB_LOCATION, 0x7fff0000);  in fixup_memory_mappings()
2059 	OUTREG(MC_AGP_LOCATION, 0xffff0000 | (agp_base >> 16));  in fixup_memory_mappings()
2061 	OUTREG(MC_AGP_LOCATION, 0xffffe000);  in fixup_memory_mappings()
2068 	OUTREG(DISPLAY_BASE_ADDR, aper_base);  in fixup_memory_mappings()
2070 		OUTREG(CRTC2_DISPLAY_BASE_ADDR, aper_base);  in fixup_memory_mappings()
2071 	OUTREG(OV0_BASE_ADDR, aper_base);  in fixup_memory_mappings()
2073 	OUTREG(DISPLAY_BASE_ADDR, 0);  in fixup_memory_mappings()
2075 		OUTREG(CRTC2_DISPLAY_BASE_ADDR, 0);  in fixup_memory_mappings()
2076 	OUTREG(OV0_BASE_ADDR, 0);  in fixup_memory_mappings()
2081 	OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl);  in fixup_memory_mappings()
2082 	OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl);  in fixup_memory_mappings()
2084 		OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl);  in fixup_memory_mappings()
2109 		OUTREG(MC_FB_LOCATION, tom);  in radeon_identify_vram()
2110 		OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);  in radeon_identify_vram()
2111 		OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);  in radeon_identify_vram()
2112 		OUTREG(OV0_BASE_ADDR, (tom & 0xffff) << 16);  in radeon_identify_vram()
2115 		OUTREG(GRPH2_BUFFER_CNTL, INREG(GRPH2_BUFFER_CNTL) & ~0x7f0000);  in radeon_identify_vram()