Lines Matching +full:anatop +full:- +full:enable +full:- +full:bit

1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2012-2014 Freescale Semiconductor, Inc.
48 #define BM_USBPHY_CTRL_SFTRST BIT(31)
49 #define BM_USBPHY_CTRL_CLKGATE BIT(30)
50 #define BM_USBPHY_CTRL_OTG_ID_VALUE BIT(27)
51 #define BM_USBPHY_CTRL_ENAUTOSET_USBCLKS BIT(26)
52 #define BM_USBPHY_CTRL_ENAUTOCLR_USBCLKGATE BIT(25)
53 #define BM_USBPHY_CTRL_ENVBUSCHG_WKUP BIT(23)
54 #define BM_USBPHY_CTRL_ENIDCHG_WKUP BIT(22)
55 #define BM_USBPHY_CTRL_ENDPDMCHG_WKUP BIT(21)
56 #define BM_USBPHY_CTRL_ENAUTOCLR_PHY_PWD BIT(20)
57 #define BM_USBPHY_CTRL_ENAUTOCLR_CLKGATE BIT(19)
58 #define BM_USBPHY_CTRL_ENAUTO_PWRON_PLL BIT(18)
59 #define BM_USBPHY_CTRL_ENUTMILEVEL3 BIT(15)
60 #define BM_USBPHY_CTRL_ENUTMILEVEL2 BIT(14)
61 #define BM_USBPHY_CTRL_ENHOSTDISCONDETECT BIT(1)
63 #define BM_USBPHY_IP_FIX (BIT(17) | BIT(18))
65 #define BM_USBPHY_DEBUG_CLKGATE BIT(30)
67 #define BM_USBPHY_PLL_LOCK BIT(31)
68 #define BM_USBPHY_PLL_REG_ENABLE BIT(21)
69 #define BM_USBPHY_PLL_BYPASS BIT(16)
70 #define BM_USBPHY_PLL_POWER BIT(12)
71 #define BM_USBPHY_PLL_EN_USB_CLKS BIT(6)
73 /* Anatop Registers */
84 #define ANADIG_USB1_CHRG_DETECT_EN_B BIT(20)
85 #define ANADIG_USB1_CHRG_DETECT_CHK_CHRG_B BIT(19)
86 #define ANADIG_USB1_CHRG_DETECT_CHK_CONTACT BIT(18)
89 #define ANADIG_USB1_VBUS_DET_STAT_VBUS_VALID BIT(3)
92 #define ANADIG_USB1_CHRG_DET_STAT_DM_STATE BIT(2)
93 #define ANADIG_USB1_CHRG_DET_STAT_CHRG_DETECTED BIT(1)
94 #define ANADIG_USB1_CHRG_DET_STAT_PLUG_CONTACT BIT(0)
100 #define ANADIG_USB1_LOOPBACK_UTMI_TESTSTART BIT(0)
108 #define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG BIT(12)
109 #define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG_SL BIT(11)
111 #define BM_ANADIG_USB1_VBUS_DET_STAT_VBUS_VALID BIT(3)
112 #define BM_ANADIG_USB2_VBUS_DET_STAT_VBUS_VALID BIT(3)
114 #define BM_ANADIG_USB1_LOOPBACK_UTMI_DIG_TST1 BIT(2)
115 #define BM_ANADIG_USB1_LOOPBACK_TSTI_TX_EN BIT(5)
116 #define BM_ANADIG_USB2_LOOPBACK_UTMI_DIG_TST1 BIT(2)
117 #define BM_ANADIG_USB2_LOOPBACK_TSTI_TX_EN BIT(5)
119 #define BM_ANADIG_USB1_MISC_RX_VPIN_FS BIT(29)
120 #define BM_ANADIG_USB1_MISC_RX_VMIN_FS BIT(28)
121 #define BM_ANADIG_USB2_MISC_RX_VPIN_FS BIT(29)
122 #define BM_ANADIG_USB2_MISC_RX_VMIN_FS BIT(28)
127 #define USB_PHY_VLLS_WAKEUP_EN BIT(0)
129 #define BM_ANADIG_REG_1P1_ENABLE_WEAK_LINREG BIT(18)
130 #define BM_ANADIG_REG_1P1_TRACK_VDD_SOC_CAP BIT(19)
135 #define MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS BIT(0)
142 #define MXS_PHY_ABNORMAL_IN_SUSPEND BIT(1)
148 #define MXS_PHY_SENDING_SOF_TOO_FAST BIT(2)
156 #define MXS_PHY_NEED_IP_FIX BIT(3)
171 #define MXS_PHY_HARDWARE_CONTROL_PHY2_CLK BIT(4)
213 { .compatible = "fsl,imx6sx-usbphy", .data = &imx6sx_phy_data, },
214 { .compatible = "fsl,imx6sl-usbphy", .data = &imx6sl_phy_data, },
215 { .compatible = "fsl,imx6q-usbphy", .data = &imx6q_phy_data, },
216 { .compatible = "fsl,imx23-usbphy", .data = &imx23_phy_data, },
217 { .compatible = "fsl,vf610-usbphy", .data = &vf610_phy_data, },
218 { .compatible = "fsl,imx6ul-usbphy", .data = &imx6ul_phy_data, },
219 { .compatible = "fsl,imx7ulp-usbphy", .data = &imx7ulp_phy_data, },
238 return mxs_phy->data == &imx6q_phy_data; in is_imx6q_phy()
243 return mxs_phy->data == &imx6sl_phy_data; in is_imx6sl_phy()
248 return mxs_phy->data == &imx7ulp_phy_data; in is_imx7ulp_phy()
253 return mxs_phy->data == &imx6ul_phy_data; in is_imx6ul_phy()
267 void __iomem *base = mxs_phy->phy.io_priv; in mxs_phy_tx_init()
271 if (mxs_phy->tx_reg_mask) { in mxs_phy_tx_init()
273 phytx &= ~mxs_phy->tx_reg_mask; in mxs_phy_tx_init()
274 phytx |= mxs_phy->tx_reg_set; in mxs_phy_tx_init()
279 static int mxs_phy_pll_enable(void __iomem *base, bool enable) in mxs_phy_pll_enable() argument
283 if (enable) { in mxs_phy_pll_enable()
311 void __iomem *base = mxs_phy->phy.io_priv; in mxs_phy_hw_init()
323 if (mxs_phy->phy_3p0) { in mxs_phy_hw_init()
324 ret = regulator_enable(mxs_phy->phy_3p0); in mxs_phy_hw_init()
326 dev_err(mxs_phy->phy.dev, in mxs_phy_hw_init()
327 "Failed to enable 3p0 regulator, ret=%d\n", in mxs_phy_hw_init()
338 * - Auto clock/power on in mxs_phy_hw_init()
339 * - Enable full/low speed support in mxs_phy_hw_init()
350 if (mxs_phy->data->flags & MXS_PHY_NEED_IP_FIX) in mxs_phy_hw_init()
353 if (mxs_phy->regmap_anatop) { in mxs_phy_hw_init()
354 unsigned int reg = mxs_phy->port_id ? in mxs_phy_hw_init()
361 regmap_write(mxs_phy->regmap_anatop, reg, in mxs_phy_hw_init()
381 if (!mxs_phy->regmap_anatop) in mxs_phy_get_vbus_status()
384 if (mxs_phy->port_id == 0) in mxs_phy_get_vbus_status()
385 regmap_read(mxs_phy->regmap_anatop, in mxs_phy_get_vbus_status()
388 else if (mxs_phy->port_id == 1) in mxs_phy_get_vbus_status()
389 regmap_read(mxs_phy->regmap_anatop, in mxs_phy_get_vbus_status()
401 void __iomem *base = mxs_phy->phy.io_priv; in __mxs_phy_disconnect_line()
408 if (mxs_phy->port_id == 0) { in __mxs_phy_disconnect_line()
411 regmap_write(mxs_phy->regmap_anatop, reg, in __mxs_phy_disconnect_line()
414 } else if (mxs_phy->port_id == 1) { in __mxs_phy_disconnect_line()
417 regmap_write(mxs_phy->regmap_anatop, reg, in __mxs_phy_disconnect_line()
433 return mxs_phy->phy.last_event == USB_EVENT_ID; in mxs_phy_is_otg_host()
439 enum usb_phy_events last_event = mxs_phy->phy.last_event; in mxs_phy_disconnect_line()
442 if (!(mxs_phy->data->flags & MXS_PHY_DISCONNECT_LINE_WITHOUT_VBUS)) in mxs_phy_disconnect_line()
445 /* If the SoCs don't have anatop, quit */ in mxs_phy_disconnect_line()
446 if (!mxs_phy->regmap_anatop) in mxs_phy_disconnect_line()
465 ret = clk_prepare_enable(mxs_phy->clk); in mxs_phy_init()
484 writel(value, phy->io_priv + HW_USBPHY_CTRL_CLR); in mxs_phy_shutdown()
485 writel(0xffffffff, phy->io_priv + HW_USBPHY_PWD); in mxs_phy_shutdown()
488 phy->io_priv + HW_USBPHY_CTRL_SET); in mxs_phy_shutdown()
491 mxs_phy_pll_enable(phy->io_priv, false); in mxs_phy_shutdown()
493 if (mxs_phy->phy_3p0) in mxs_phy_shutdown()
494 regulator_disable(mxs_phy->phy_3p0); in mxs_phy_shutdown()
496 clk_disable_unprepare(mxs_phy->clk); in mxs_phy_shutdown()
502 /* bit definition is the same for all controllers */ in mxs_phy_is_low_speed_connection()
507 /* If the SoCs don't have anatop, quit */ in mxs_phy_is_low_speed_connection()
508 if (!mxs_phy->regmap_anatop) in mxs_phy_is_low_speed_connection()
511 if (mxs_phy->port_id == 0) in mxs_phy_is_low_speed_connection()
513 else if (mxs_phy->port_id == 1) in mxs_phy_is_low_speed_connection()
516 regmap_read(mxs_phy->regmap_anatop, reg, &line_state); in mxs_phy_is_low_speed_connection()
535 * FIXME: Do not power down RXPWD1PT1 bit for low speed in mxs_phy_suspend()
545 writel(0xffbfffff, x->io_priv + HW_USBPHY_PWD); in mxs_phy_suspend()
547 writel(0xffffffff, x->io_priv + HW_USBPHY_PWD); in mxs_phy_suspend()
550 x->io_priv + HW_USBPHY_CTRL_SET); in mxs_phy_suspend()
551 if (!(mxs_phy->port_id == 1 && in mxs_phy_suspend()
552 (mxs_phy->data->flags & in mxs_phy_suspend()
554 clk_disable_unprepare(mxs_phy->clk); in mxs_phy_suspend()
557 if (!(mxs_phy->port_id == 1 && in mxs_phy_suspend()
558 (mxs_phy->data->flags & in mxs_phy_suspend()
560 ret = clk_prepare_enable(mxs_phy->clk); in mxs_phy_suspend()
565 x->io_priv + HW_USBPHY_CTRL_CLR); in mxs_phy_suspend()
566 writel(0, x->io_priv + HW_USBPHY_PWD); in mxs_phy_suspend()
580 writel_relaxed(value, x->io_priv + HW_USBPHY_CTRL_SET); in mxs_phy_set_wakeup()
582 writel_relaxed(value, x->io_priv + HW_USBPHY_CTRL_CLR); in mxs_phy_set_wakeup()
592 dev_dbg(phy->dev, "%s device has connected\n", in mxs_phy_on_connect()
597 phy->io_priv + HW_USBPHY_CTRL_SET); in mxs_phy_on_connect()
605 dev_dbg(phy->dev, "%s device has disconnected\n", in mxs_phy_on_disconnect()
609 if (readl(phy->io_priv + HW_USBPHY_CTRL) & in mxs_phy_on_disconnect()
612 phy->io_priv + HW_USBPHY_CTRL_CLR); in mxs_phy_on_disconnect()
620 struct regmap *regmap = x->regmap_anatop; in mxs_charger_data_contact_detect()
627 dev_err(x->phy.dev, "vbus is not valid\n"); in mxs_charger_data_contact_detect()
628 return -EINVAL; in mxs_charger_data_contact_detect()
631 /* Enable charger detector */ in mxs_charger_data_contact_detect()
635 * - Do not check whether a charger is connected to the USB port in mxs_charger_data_contact_detect()
636 * - Check whether the USB plug has been in contact with each other in mxs_charger_data_contact_detect()
659 dev_err(x->phy.dev, in mxs_charger_data_contact_detect()
665 return -ENXIO; in mxs_charger_data_contact_detect()
673 struct regmap *regmap = x->regmap_anatop; in mxs_charger_primary_detection()
678 * - Do check whether a charger is connected to the USB port in mxs_charger_primary_detection()
679 * - Do not Check whether the USB plug has been in contact with in mxs_charger_primary_detection()
692 dev_dbg(x->phy.dev, "It is a standard downstream port\n"); in mxs_charger_primary_detection()
709 struct regmap *regmap = x->regmap_anatop; in mxs_charger_secondary_detection()
716 dev_dbg(x->phy.dev, "It is a dedicate charging port\n"); in mxs_charger_secondary_detection()
719 dev_dbg(x->phy.dev, "It is a charging downstream port\n"); in mxs_charger_secondary_detection()
727 struct regmap *regmap = mxs_phy->regmap_anatop; in mxs_phy_charger_detect()
728 void __iomem *base = phy->io_priv; in mxs_phy_charger_detect()
764 struct device_node *np = pdev->dev.of_node; in mxs_phy_probe()
771 clk = devm_clk_get(&pdev->dev, NULL); in mxs_phy_probe()
773 dev_err(&pdev->dev, in mxs_phy_probe()
778 mxs_phy = devm_kzalloc(&pdev->dev, sizeof(*mxs_phy), GFP_KERNEL); in mxs_phy_probe()
780 return -ENOMEM; in mxs_phy_probe()
782 /* Some SoCs don't have anatop registers */ in mxs_phy_probe()
783 if (of_property_present(np, "fsl,anatop")) { in mxs_phy_probe()
784 mxs_phy->regmap_anatop = syscon_regmap_lookup_by_phandle in mxs_phy_probe()
785 (np, "fsl,anatop"); in mxs_phy_probe()
786 if (IS_ERR(mxs_phy->regmap_anatop)) { in mxs_phy_probe()
787 dev_dbg(&pdev->dev, in mxs_phy_probe()
788 "failed to find regmap for anatop\n"); in mxs_phy_probe()
789 return PTR_ERR(mxs_phy->regmap_anatop); in mxs_phy_probe()
795 mxs_phy->regmap_sim = syscon_regmap_lookup_by_phandle in mxs_phy_probe()
797 if (IS_ERR(mxs_phy->regmap_sim)) { in mxs_phy_probe()
798 dev_dbg(&pdev->dev, in mxs_phy_probe()
800 return PTR_ERR(mxs_phy->regmap_sim); in mxs_phy_probe()
805 if (!of_property_read_u32(np, "fsl,tx-cal-45-dn-ohms", &val) && in mxs_phy_probe()
807 /* Scale to a 4-bit value */ in mxs_phy_probe()
808 val = (MXS_PHY_TX_CAL45_MAX - val) * 0xF in mxs_phy_probe()
809 / (MXS_PHY_TX_CAL45_MAX - MXS_PHY_TX_CAL45_MIN); in mxs_phy_probe()
810 mxs_phy->tx_reg_mask |= GM_USBPHY_TX_TXCAL45DN(~0); in mxs_phy_probe()
811 mxs_phy->tx_reg_set |= GM_USBPHY_TX_TXCAL45DN(val); in mxs_phy_probe()
814 if (!of_property_read_u32(np, "fsl,tx-cal-45-dp-ohms", &val) && in mxs_phy_probe()
816 /* Scale to a 4-bit value. */ in mxs_phy_probe()
817 val = (MXS_PHY_TX_CAL45_MAX - val) * 0xF in mxs_phy_probe()
818 / (MXS_PHY_TX_CAL45_MAX - MXS_PHY_TX_CAL45_MIN); in mxs_phy_probe()
819 mxs_phy->tx_reg_mask |= GM_USBPHY_TX_TXCAL45DP(~0); in mxs_phy_probe()
820 mxs_phy->tx_reg_set |= GM_USBPHY_TX_TXCAL45DP(val); in mxs_phy_probe()
823 if (!of_property_read_u32(np, "fsl,tx-d-cal", &val) && in mxs_phy_probe()
825 /* Scale to a 4-bit value. Round up the values and heavily in mxs_phy_probe()
828 val = ((MXS_PHY_TX_D_CAL_MAX - val) * 0xF in mxs_phy_probe()
829 + (MXS_PHY_TX_D_CAL_MAX - MXS_PHY_TX_D_CAL_MIN) * 2/3) in mxs_phy_probe()
830 / (MXS_PHY_TX_D_CAL_MAX - MXS_PHY_TX_D_CAL_MIN); in mxs_phy_probe()
831 mxs_phy->tx_reg_mask |= GM_USBPHY_TX_D_CAL(~0); in mxs_phy_probe()
832 mxs_phy->tx_reg_set |= GM_USBPHY_TX_D_CAL(val); in mxs_phy_probe()
837 dev_dbg(&pdev->dev, "failed to get alias id, errno %d\n", ret); in mxs_phy_probe()
838 mxs_phy->port_id = ret; in mxs_phy_probe()
840 mxs_phy->phy.io_priv = base; in mxs_phy_probe()
841 mxs_phy->phy.dev = &pdev->dev; in mxs_phy_probe()
842 mxs_phy->phy.label = DRIVER_NAME; in mxs_phy_probe()
843 mxs_phy->phy.init = mxs_phy_init; in mxs_phy_probe()
844 mxs_phy->phy.shutdown = mxs_phy_shutdown; in mxs_phy_probe()
845 mxs_phy->phy.set_suspend = mxs_phy_suspend; in mxs_phy_probe()
846 mxs_phy->phy.notify_connect = mxs_phy_on_connect; in mxs_phy_probe()
847 mxs_phy->phy.notify_disconnect = mxs_phy_on_disconnect; in mxs_phy_probe()
848 mxs_phy->phy.type = USB_PHY_TYPE_USB2; in mxs_phy_probe()
849 mxs_phy->phy.set_wakeup = mxs_phy_set_wakeup; in mxs_phy_probe()
850 mxs_phy->phy.charger_detect = mxs_phy_charger_detect; in mxs_phy_probe()
852 mxs_phy->clk = clk; in mxs_phy_probe()
853 mxs_phy->data = of_device_get_match_data(&pdev->dev); in mxs_phy_probe()
855 mxs_phy->phy_3p0 = devm_regulator_get(&pdev->dev, "phy-3p0"); in mxs_phy_probe()
856 if (PTR_ERR(mxs_phy->phy_3p0) == -ENODEV) in mxs_phy_probe()
858 mxs_phy->phy_3p0 = NULL; in mxs_phy_probe()
859 else if (IS_ERR(mxs_phy->phy_3p0)) in mxs_phy_probe()
860 return dev_err_probe(&pdev->dev, PTR_ERR(mxs_phy->phy_3p0), in mxs_phy_probe()
863 if (mxs_phy->phy_3p0) in mxs_phy_probe()
864 regulator_set_voltage(mxs_phy->phy_3p0, 3200000, 3200000); in mxs_phy_probe()
868 device_set_wakeup_capable(&pdev->dev, true); in mxs_phy_probe()
870 return usb_add_phy_dev(&mxs_phy->phy); in mxs_phy_probe()
877 usb_remove_phy(&mxs_phy->phy); in mxs_phy_remove()
886 if (!mxs_phy->regmap_sim) in mxs_phy_wakeup_enable()
890 regmap_update_bits(mxs_phy->regmap_sim, SIM_GPR1, mask, mask); in mxs_phy_wakeup_enable()
893 regmap_update_bits(mxs_phy->regmap_sim, SIM_GPR1, mask, 0); in mxs_phy_wakeup_enable()
902 /* If the SoCs don't have anatop, quit */ in mxs_phy_enable_ldo_in_suspend()
903 if (!mxs_phy->regmap_anatop) in mxs_phy_enable_ldo_in_suspend()
908 regmap_write(mxs_phy->regmap_anatop, reg, in mxs_phy_enable_ldo_in_suspend()
912 regmap_write(mxs_phy->regmap_anatop, in mxs_phy_enable_ldo_in_suspend()
919 regmap_write(mxs_phy->regmap_anatop, reg, value); in mxs_phy_enable_ldo_in_suspend()
921 regmap_write(mxs_phy->regmap_anatop, reg, value); in mxs_phy_enable_ldo_in_suspend()
975 MODULE_ALIAS("platform:mxs-usb-phy");