Lines Matching +full:0 +full:x07ffffff
12 /* VLYNQ control register. 32-bit at offset 0x000 */
13 #define TUSB_VLYNQ_CTRL 0x004
15 /* Mentor Graphics OTG core registers. 8,- 16- and 32-bit at offset 0x400 */
16 #define TUSB_BASE_OFFSET 0x400
18 /* FIFO registers 32-bit at offset 0x600 */
19 #define TUSB_FIFO_BASE 0x600
21 /* Device System & Control registers. 32-bit at offset 0x800 */
22 #define TUSB_SYS_REG_BASE 0x800
24 #define TUSB_DEV_CONF (TUSB_SYS_REG_BASE + 0x000)
28 #define TUSB_DEV_CONF_ID_SEL (1 << 0)
30 #define TUSB_PHY_OTG_CTRL_ENABLE (TUSB_SYS_REG_BASE + 0x004)
31 #define TUSB_PHY_OTG_CTRL (TUSB_SYS_REG_BASE + 0x008)
32 #define TUSB_PHY_OTG_CTRL_WRPROTECT (0xa5 << 24)
52 #define TUSB_PHY_OTG_CTRL_CLK_MODE (1 << 0)
55 #define TUSB_DEV_OTG_STAT (TUSB_SYS_REG_BASE + 0x00c)
63 #define TUSB_DEV_OTG_STAT_LINE_STATE (3 << 0)
65 #define TUSB_DEV_OTG_STAT_DM_ENABLE (1 << 0)
67 #define TUSB_DEV_OTG_TIMER (TUSB_SYS_REG_BASE + 0x010)
69 # define TUSB_DEV_OTG_TIMER_VAL(v) ((v) & 0x07ffffff)
70 #define TUSB_PRCM_REV (TUSB_SYS_REG_BASE + 0x014)
73 #define TUSB_PRCM_CONF (TUSB_SYS_REG_BASE + 0x018)
78 #define TUSB_PRCM_MNGMT (TUSB_SYS_REG_BASE + 0x01c)
79 #define TUSB_PRCM_MNGMT_SRP_FIX_TIMER(v) (((v) & 0xf) << 25)
81 #define TUSB_PRCM_MNGMT_VBUS_VALID_TIMER(v) (((v) & 0xf) << 20)
92 #define TUSB_PRCM_MNGMT_DEV_IDLE (1 << 0)
95 #define TUSB_PRCM_WAKEUP_SOURCE (TUSB_SYS_REG_BASE + 0x020)
96 #define TUSB_PRCM_WAKEUP_CLEAR (TUSB_SYS_REG_BASE + 0x028)
97 #define TUSB_PRCM_WAKEUP_MASK (TUSB_SYS_REG_BASE + 0x02c)
98 #define TUSB_PRCM_WAKEUP_RESERVED_BITS (0xffffe << 13)
111 #define TUSB_PRCM_WID (1 << 0) /* OTG PHY ID detect */
113 #define TUSB_PULLUP_1_CTRL (TUSB_SYS_REG_BASE + 0x030)
114 #define TUSB_PULLUP_2_CTRL (TUSB_SYS_REG_BASE + 0x034)
115 #define TUSB_INT_CTRL_REV (TUSB_SYS_REG_BASE + 0x038)
116 #define TUSB_INT_CTRL_CONF (TUSB_SYS_REG_BASE + 0x03c)
117 #define TUSB_USBIP_INT_SRC (TUSB_SYS_REG_BASE + 0x040)
118 #define TUSB_USBIP_INT_SET (TUSB_SYS_REG_BASE + 0x044)
119 #define TUSB_USBIP_INT_CLEAR (TUSB_SYS_REG_BASE + 0x048)
120 #define TUSB_USBIP_INT_MASK (TUSB_SYS_REG_BASE + 0x04c)
121 #define TUSB_DMA_INT_SRC (TUSB_SYS_REG_BASE + 0x050)
122 #define TUSB_DMA_INT_SET (TUSB_SYS_REG_BASE + 0x054)
123 #define TUSB_DMA_INT_CLEAR (TUSB_SYS_REG_BASE + 0x058)
124 #define TUSB_DMA_INT_MASK (TUSB_SYS_REG_BASE + 0x05c)
125 #define TUSB_GPIO_INT_SRC (TUSB_SYS_REG_BASE + 0x060)
126 #define TUSB_GPIO_INT_SET (TUSB_SYS_REG_BASE + 0x064)
127 #define TUSB_GPIO_INT_CLEAR (TUSB_SYS_REG_BASE + 0x068)
128 #define TUSB_GPIO_INT_MASK (TUSB_SYS_REG_BASE + 0x06c)
131 #define TUSB_INT_SRC (TUSB_SYS_REG_BASE + 0x070)
132 #define TUSB_INT_SRC_SET (TUSB_SYS_REG_BASE + 0x074)
133 #define TUSB_INT_SRC_CLEAR (TUSB_SYS_REG_BASE + 0x078)
134 #define TUSB_INT_MASK (TUSB_SYS_REG_BASE + 0x07c)
151 #define TUSB_INT_SRC_USB_IP_SUSPEND (1 << 0)
153 /* NOR flash interrupt registers reserved bits. Must be written as 0 */
154 #define TUSB_INT_MASK_RESERVED_17 (0x3fff << 17)
156 #define TUSB_INT_MASK_RESERVED_8 (0xf << 8)
157 #define TUSB_INT_SRC_RESERVED_26 (0x1f << 26)
158 #define TUSB_INT_SRC_RESERVED_18 (0x3f << 18)
159 #define TUSB_INT_SRC_RESERVED_10 (0x03 << 10)
171 #define TUSB_GPIO_REV (TUSB_SYS_REG_BASE + 0x080)
172 #define TUSB_GPIO_CONF (TUSB_SYS_REG_BASE + 0x084)
173 #define TUSB_DMA_CTRL_REV (TUSB_SYS_REG_BASE + 0x100)
174 #define TUSB_DMA_REQ_CONF (TUSB_SYS_REG_BASE + 0x104)
175 #define TUSB_EP0_CONF (TUSB_SYS_REG_BASE + 0x108)
176 #define TUSB_DMA_EP_MAP (TUSB_SYS_REG_BASE + 0x148)
179 #define TUSB_EP_TX_OFFSET 0x10c /* EP_IN in docs */
180 #define TUSB_EP_RX_OFFSET 0x14c /* EP_OUT in docs */
181 #define TUSB_EP_MAX_PACKET_SIZE_OFFSET 0x188
183 #define TUSB_WAIT_COUNT (TUSB_SYS_REG_BASE + 0x1c8)
184 #define TUSB_SCRATCH_PAD (TUSB_SYS_REG_BASE + 0x1c4)
185 #define TUSB_PROD_TEST_RESET (TUSB_SYS_REG_BASE + 0x1d8)
188 #define TUSB_INT_CTRL_CONF_INT_RELCYC(v) (((v) & 0x7) << 18)
191 #define TUSB_GPIO_CONF_DMAREQ(v) (((v) & 0x3f) << 24)
193 #define TUSB_DMA_REQ_CONF_DMA_REQ_EN(v) (((v) & 0x3f) << 20)
194 #define TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(v) (((v) & 0xf) << 16)
197 #define TUSB_EP0_CONFIG_XFR_SIZE(v) ((v) & 0x7f)
199 #define TUSB_EP_CONFIG_XFR_SIZE(v) ((v) & 0x7fffffff)
200 #define TUSB_PROD_TEST_RESET_VAL 0xa596
201 #define TUSB_EP_FIFO(ep) (TUSB_FIFO_BASE + (ep) * 0x20)
203 #define TUSB_DIDR1_LO (TUSB_SYS_REG_BASE + 0x1f8)
204 #define TUSB_DIDR1_HI (TUSB_SYS_REG_BASE + 0x1fc)
205 #define TUSB_DIDR1_HI_CHIP_REV(v) (((v) >> 17) & 0xf)
206 #define TUSB_DIDR1_HI_REV_20 0
210 #define TUSB_REV_10 0x10
211 #define TUSB_REV_20 0x20
212 #define TUSB_REV_30 0x30
213 #define TUSB_REV_31 0x31