Lines Matching full:csr
90 u16 csr; in musb_h_tx_flush_fifo() local
93 csr = musb_readw(epio, MUSB_TXCSR); in musb_h_tx_flush_fifo()
94 while (csr & MUSB_TXCSR_FIFONOTEMPTY) { in musb_h_tx_flush_fifo()
95 csr |= MUSB_TXCSR_FLUSHFIFO | MUSB_TXCSR_TXPKTRDY; in musb_h_tx_flush_fifo()
96 musb_writew(epio, MUSB_TXCSR, csr); in musb_h_tx_flush_fifo()
97 csr = musb_readw(epio, MUSB_TXCSR); in musb_h_tx_flush_fifo()
114 "Could not flush host TX%d fifo: csr: %04x\n", in musb_h_tx_flush_fifo()
115 ep->epnum, csr)) in musb_h_tx_flush_fifo()
124 u16 csr; in musb_h_ep0_flush_fifo() local
129 csr = musb_readw(epio, MUSB_TXCSR); in musb_h_ep0_flush_fifo()
130 if (!(csr & (MUSB_CSR0_TXPKTRDY | MUSB_CSR0_RXPKTRDY))) in musb_h_ep0_flush_fifo()
133 csr = musb_readw(epio, MUSB_TXCSR); in musb_h_ep0_flush_fifo()
137 WARN(!retries, "Could not flush host TX%d fifo: csr: %04x\n", in musb_h_ep0_flush_fifo()
138 ep->epnum, csr); in musb_h_ep0_flush_fifo()
390 static u16 musb_h_flush_rxfifo(struct musb_hw_ep *hw_ep, u16 csr) in musb_h_flush_rxfifo() argument
396 csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_RXPKTRDY; in musb_h_flush_rxfifo()
397 csr &= ~(MUSB_RXCSR_H_REQPKT in musb_h_flush_rxfifo()
402 musb_writew(hw_ep->regs, MUSB_RXCSR, csr); in musb_h_flush_rxfifo()
403 musb_writew(hw_ep->regs, MUSB_RXCSR, csr); in musb_h_flush_rxfifo()
417 u16 csr; in musb_host_packet_rx() local
490 csr = musb_readw(epio, MUSB_RXCSR); in musb_host_packet_rx()
491 csr |= MUSB_RXCSR_H_WZC_BITS; in musb_host_packet_rx()
493 musb_h_flush_rxfifo(hw_ep, csr); in musb_host_packet_rx()
496 csr &= ~(MUSB_RXCSR_RXPKTRDY | MUSB_RXCSR_H_REQPKT); in musb_host_packet_rx()
498 csr |= MUSB_RXCSR_H_REQPKT; in musb_host_packet_rx()
499 musb_writew(epio, MUSB_RXCSR, csr); in musb_host_packet_rx()
506 * when we do, use tx/rx reinit routine and then construct a new CSR
517 u16 csr; in musb_rx_reinit() local
526 csr = musb_readw(ep->regs, MUSB_TXCSR); in musb_rx_reinit()
527 if (csr & MUSB_TXCSR_MODE) { in musb_rx_reinit()
529 csr = musb_readw(ep->regs, MUSB_TXCSR); in musb_rx_reinit()
531 csr | MUSB_TXCSR_FRCDATATOG); in musb_rx_reinit()
538 if (csr & MUSB_TXCSR_DMAMODE) in musb_rx_reinit()
544 csr = musb_readw(ep->regs, MUSB_RXCSR); in musb_rx_reinit()
545 if (csr & MUSB_RXCSR_RXPKTRDY) in musb_rx_reinit()
579 u16 csr; in musb_tx_dma_set_mode_mentor() local
584 csr = musb_readw(epio, MUSB_TXCSR); in musb_tx_dma_set_mode_mentor()
587 csr |= MUSB_TXCSR_DMAMODE | MUSB_TXCSR_DMAENAB; in musb_tx_dma_set_mode_mentor()
600 csr |= MUSB_TXCSR_AUTOSET; in musb_tx_dma_set_mode_mentor()
603 csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAMODE); in musb_tx_dma_set_mode_mentor()
604 csr |= MUSB_TXCSR_DMAENAB; /* against programmer's guide */ in musb_tx_dma_set_mode_mentor()
607 musb_writew(epio, MUSB_TXCSR, csr); in musb_tx_dma_set_mode_mentor()
652 u16 csr; in musb_tx_dma_program() local
657 csr = musb_readw(epio, MUSB_TXCSR); in musb_tx_dma_program()
658 csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB); in musb_tx_dma_program()
659 musb_writew(epio, MUSB_TXCSR, csr | MUSB_TXCSR_H_WZC_BITS); in musb_tx_dma_program()
682 u16 csr; in musb_ep_program() local
696 csr = musb_readw(epio, MUSB_TXCSR); in musb_ep_program()
697 csr &= ~MUSB_TXCSR_DMAENAB; in musb_ep_program()
698 musb_writew(epio, MUSB_TXCSR, csr); in musb_ep_program()
721 u16 csr; in musb_ep_program() local
725 csr = musb_readw(epio, MUSB_TXCSR); in musb_ep_program()
747 csr &= ~(MUSB_TXCSR_H_NAKTIMEOUT in musb_ep_program()
755 csr |= MUSB_TXCSR_MODE; in musb_ep_program()
758 csr |= musb->io.set_toggle(qh, is_out, urb); in musb_ep_program()
760 musb_writew(epio, MUSB_TXCSR, csr); in musb_ep_program()
762 csr &= ~MUSB_TXCSR_DMAMODE; in musb_ep_program()
763 musb_writew(epio, MUSB_TXCSR, csr); in musb_ep_program()
764 csr = musb_readw(epio, MUSB_TXCSR); in musb_ep_program()
840 u16 csr = 0; in musb_ep_program() local
844 csr |= musb->io.set_toggle(qh, is_out, urb); in musb_ep_program()
847 csr |= MUSB_RXCSR_DISNYET; in musb_ep_program()
850 csr = musb_readw(hw_ep->regs, MUSB_RXCSR); in musb_ep_program()
852 if (csr & (MUSB_RXCSR_RXPKTRDY in musb_ep_program()
855 ERR("broken !rx_reinit, ep%d csr %04x\n", in musb_ep_program()
856 hw_ep->epnum, csr); in musb_ep_program()
859 csr &= MUSB_RXCSR_DISNYET; in musb_ep_program()
870 musb_writew(hw_ep->regs, MUSB_RXCSR, csr); in musb_ep_program()
871 csr = musb_readw(hw_ep->regs, MUSB_RXCSR); in musb_ep_program()
886 csr |= MUSB_RXCSR_DMAENAB; in musb_ep_program()
889 csr |= MUSB_RXCSR_H_REQPKT; in musb_ep_program()
890 musb_dbg(musb, "RXCSR%d := %04x", epnum, csr); in musb_ep_program()
891 musb_writew(hw_ep->regs, MUSB_RXCSR, csr); in musb_ep_program()
892 csr = musb_readw(hw_ep->regs, MUSB_RXCSR); in musb_ep_program()
1057 u16 csr, len; in musb_h_ep0_irq() local
1070 csr = musb_readw(epio, MUSB_CSR0); in musb_h_ep0_irq()
1071 len = (csr & MUSB_CSR0_RXPKTRDY) in musb_h_ep0_irq()
1076 csr, qh, len, urb, musb->ep0_stage); in musb_h_ep0_irq()
1085 if (csr & MUSB_CSR0_H_RXSTALL) { in musb_h_ep0_irq()
1089 } else if (csr & MUSB_CSR0_H_ERROR) { in musb_h_ep0_irq()
1090 musb_dbg(musb, "no response, csr0 %04x", csr); in musb_h_ep0_irq()
1093 } else if (csr & MUSB_CSR0_H_NAKTIMEOUT) { in musb_h_ep0_irq()
1116 if (csr & MUSB_CSR0_H_REQPKT) { in musb_h_ep0_irq()
1117 csr &= ~MUSB_CSR0_H_REQPKT; in musb_h_ep0_irq()
1118 musb_writew(epio, MUSB_CSR0, csr); in musb_h_ep0_irq()
1119 csr &= ~MUSB_CSR0_H_NAKTIMEOUT; in musb_h_ep0_irq()
1120 musb_writew(epio, MUSB_CSR0, csr); in musb_h_ep0_irq()
1144 csr = (MUSB_EP0_IN == musb->ep0_stage) in musb_h_ep0_irq()
1150 csr = MUSB_CSR0_H_STATUSPKT in musb_h_ep0_irq()
1153 csr = MUSB_CSR0_H_STATUSPKT in musb_h_ep0_irq()
1157 csr |= MUSB_CSR0_H_DIS_PING; in musb_h_ep0_irq()
1162 musb_dbg(musb, "ep0 STATUS, csr %04x", csr); in musb_h_ep0_irq()
1165 musb_writew(epio, MUSB_CSR0, csr); in musb_h_ep0_irq()
1216 musb_dbg(musb, "extra TX%d ready, csr %04x", epnum, tx_csr); in musb_host_tx()
1223 musb_dbg(musb, "OUT/TX%d end, csr %04x%s", epnum, tx_csr, in musb_host_tx()
1292 musb_dbg(musb, "extra TX%d ready, csr %04x", epnum, tx_csr); in musb_host_tx()
1352 "DMA complete but FIFO not empty, CSR %04x", in musb_host_tx()
1760 musb_dbg(musb, "BOGUS RX%d ready, csr %04x, count %d", in musb_host_rx()
1843 ERR("RX%d dma busy, csr %04x\n", epnum, rx_csr); in musb_host_rx()
2317 u16 csr; in musb_cleanup_urb() local
2336 csr = musb_h_flush_rxfifo(ep, 0); in musb_cleanup_urb()
2343 csr = musb_readw(epio, MUSB_TXCSR); in musb_cleanup_urb()
2344 csr &= ~(MUSB_TXCSR_AUTOSET in musb_cleanup_urb()
2350 musb_writew(epio, MUSB_TXCSR, csr); in musb_cleanup_urb()
2352 musb_writew(epio, MUSB_TXCSR, csr); in musb_cleanup_urb()
2354 csr = musb_readw(epio, MUSB_TXCSR); in musb_cleanup_urb()