Lines Matching +full:0 +full:x0c08
14 #define SSUSB_DEV_BASE 0x0000
15 #define SSUSB_EPCTL_CSR_BASE 0x0800
16 #define SSUSB_USB3_MAC_CSR_BASE 0x1400
17 #define SSUSB_USB3_SYS_CSR_BASE 0x1400
18 #define SSUSB_USB2_CSR_BASE 0x2400
21 #define SSUSB_SIFSLV_IPPC_BASE 0x0000
25 #define U3D_LV1ISR (SSUSB_DEV_BASE + 0x0000)
26 #define U3D_LV1IER (SSUSB_DEV_BASE + 0x0004)
27 #define U3D_LV1IESR (SSUSB_DEV_BASE + 0x0008)
28 #define U3D_LV1IECR (SSUSB_DEV_BASE + 0x000C)
30 #define U3D_EPISR (SSUSB_DEV_BASE + 0x0080)
31 #define U3D_EPIER (SSUSB_DEV_BASE + 0x0084)
32 #define U3D_EPIESR (SSUSB_DEV_BASE + 0x0088)
33 #define U3D_EPIECR (SSUSB_DEV_BASE + 0x008C)
35 #define U3D_EP0CSR (SSUSB_DEV_BASE + 0x0100)
36 #define U3D_RXCOUNT0 (SSUSB_DEV_BASE + 0x0108)
37 #define U3D_RESERVED (SSUSB_DEV_BASE + 0x010C)
38 #define U3D_TX1CSR0 (SSUSB_DEV_BASE + 0x0110)
39 #define U3D_TX1CSR1 (SSUSB_DEV_BASE + 0x0114)
40 #define U3D_TX1CSR2 (SSUSB_DEV_BASE + 0x0118)
42 #define U3D_RX1CSR0 (SSUSB_DEV_BASE + 0x0210)
43 #define U3D_RX1CSR1 (SSUSB_DEV_BASE + 0x0214)
44 #define U3D_RX1CSR2 (SSUSB_DEV_BASE + 0x0218)
46 #define U3D_FIFO0 (SSUSB_DEV_BASE + 0x0300)
48 #define U3D_QCR0 (SSUSB_DEV_BASE + 0x0400)
49 #define U3D_QCR1 (SSUSB_DEV_BASE + 0x0404)
50 #define U3D_QCR2 (SSUSB_DEV_BASE + 0x0408)
51 #define U3D_QCR3 (SSUSB_DEV_BASE + 0x040C)
52 #define U3D_QFCR (SSUSB_DEV_BASE + 0x0428)
53 #define U3D_TXQHIAR1 (SSUSB_DEV_BASE + 0x0484)
54 #define U3D_RXQHIAR1 (SSUSB_DEV_BASE + 0x04C4)
56 #define U3D_TXQCSR1 (SSUSB_DEV_BASE + 0x0510)
57 #define U3D_TXQSAR1 (SSUSB_DEV_BASE + 0x0514)
58 #define U3D_TXQCPR1 (SSUSB_DEV_BASE + 0x0518)
60 #define U3D_RXQCSR1 (SSUSB_DEV_BASE + 0x0610)
61 #define U3D_RXQSAR1 (SSUSB_DEV_BASE + 0x0614)
62 #define U3D_RXQCPR1 (SSUSB_DEV_BASE + 0x0618)
63 #define U3D_RXQLDPR1 (SSUSB_DEV_BASE + 0x061C)
65 #define U3D_QISAR0 (SSUSB_DEV_BASE + 0x0700)
66 #define U3D_QIER0 (SSUSB_DEV_BASE + 0x0704)
67 #define U3D_QIESR0 (SSUSB_DEV_BASE + 0x0708)
68 #define U3D_QIECR0 (SSUSB_DEV_BASE + 0x070C)
69 #define U3D_QISAR1 (SSUSB_DEV_BASE + 0x0710)
70 #define U3D_QIER1 (SSUSB_DEV_BASE + 0x0714)
71 #define U3D_QIESR1 (SSUSB_DEV_BASE + 0x0718)
72 #define U3D_QIECR1 (SSUSB_DEV_BASE + 0x071C)
74 #define U3D_TQERRIR0 (SSUSB_DEV_BASE + 0x0780)
75 #define U3D_TQERRIER0 (SSUSB_DEV_BASE + 0x0784)
76 #define U3D_TQERRIESR0 (SSUSB_DEV_BASE + 0x0788)
77 #define U3D_TQERRIECR0 (SSUSB_DEV_BASE + 0x078C)
78 #define U3D_RQERRIR0 (SSUSB_DEV_BASE + 0x07C0)
79 #define U3D_RQERRIER0 (SSUSB_DEV_BASE + 0x07C4)
80 #define U3D_RQERRIESR0 (SSUSB_DEV_BASE + 0x07C8)
81 #define U3D_RQERRIECR0 (SSUSB_DEV_BASE + 0x07CC)
82 #define U3D_RQERRIR1 (SSUSB_DEV_BASE + 0x07D0)
83 #define U3D_RQERRIER1 (SSUSB_DEV_BASE + 0x07D4)
84 #define U3D_RQERRIESR1 (SSUSB_DEV_BASE + 0x07D8)
85 #define U3D_RQERRIECR1 (SSUSB_DEV_BASE + 0x07DC)
87 #define U3D_CAP_EP0FFSZ (SSUSB_DEV_BASE + 0x0C04)
88 #define U3D_CAP_EPNTXFFSZ (SSUSB_DEV_BASE + 0x0C08)
89 #define U3D_CAP_EPNRXFFSZ (SSUSB_DEV_BASE + 0x0C0C)
90 #define U3D_CAP_EPINFO (SSUSB_DEV_BASE + 0x0C10)
91 #define U3D_MISC_CTRL (SSUSB_DEV_BASE + 0x0C84)
101 #define BMU_INTR BIT(0)
104 #define LV1IECR_MSK GENMASK(31, 0)
109 #define EPTISR(x) (BIT(0) << (x))
110 #define EP0ISR BIT(0)
121 #define EP0_MAXPKTSZ_MSK GENMASK(9, 0)
133 #define TX_TXMAXPKTSZ_MSK GENMASK(10, 0)
138 #define TX_MAX_PKT_G2(x) (((x) & 0xff) << 24)
139 #define TX_MULT_G2(x) (((x) & 0x7) << 21)
140 #define TX_MULT_OG(x) (((x) & 0x3) << 22)
141 #define TX_MAX_PKT_OG(x) (((x) & 0x3f) << 16)
142 #define TX_SLOT(x) (((x) & 0x3f) << 8)
143 #define TX_TYPE(x) (((x) & 0x3) << 4)
144 #define TX_SS_BURST(x) (((x) & 0xf) << 0)
157 #define TYPE_BULK (0x0)
158 #define TYPE_INT (0x1)
159 #define TYPE_ISO (0x2)
160 #define TYPE_MASK (0x3)
163 #define TX_BINTERVAL(x) (((x) & 0xff) << 24)
164 #define TX_FIFOSEGSIZE(x) (((x) & 0xf) << 16)
165 #define TX_FIFOADDR(x) (((x) & 0x1fff) << 0)
172 #define RX_RXMAXPKTSZ_MSK GENMASK(10, 0)
177 #define RX_MAX_PKT_G2(x) (((x) & 0xff) << 24)
178 #define RX_MULT_G2(x) (((x) & 0x7) << 21)
179 #define RX_MULT_OG(x) (((x) & 0x3) << 22)
180 #define RX_MAX_PKT_OG(x) (((x) & 0x3f) << 16)
181 #define RX_SLOT(x) (((x) & 0x3f) << 8)
182 #define RX_TYPE(x) (((x) & 0x3) << 4)
183 #define RX_SS_BURST(x) (((x) & 0xf) << 0)
196 #define RX_BINTERVAL(x) (((x) & 0xff) << 24)
197 #define RX_FIFOSEGSIZE(x) (((x) & 0xf) << 16)
198 #define RX_FIFOADDR(x) (((x) & 0x1fff) << 0)
202 #define QMU_TX_CS_EN(x) (BIT(0) << (x))
203 #define QMU_CS16B_EN BIT(0)
206 #define QMU_TX_ZLP(x) (BIT(0) << (x))
210 #define QMU_RX_ZLP(x) (BIT(0) << (x))
214 #define QMU_LAST_DONE_PTR_HI(x) (((x) >> 16) & 0xf)
215 #define QMU_CUR_GPD_ADDR_HI(x) (((x) >> 8) & 0xf)
216 #define QMU_START_ADDR_HI_MSK GENMASK(3, 0)
217 #define QMU_START_ADDR_HI(x) (((x) & 0xf) << 0)
224 #define QMU_Q_START BIT(0)
228 #define QMU_TX_DONE_INT(x) (BIT(0) << (x))
237 #define TXQ_EMPTY_INT BIT(0)
241 #define QMU_TX_CS_ERR(x) (BIT(0) << (x))
245 #define QMU_RX_CS_ERR(x) (BIT(0) << (x))
251 #define CAP_RX_EP_NUM(x) (((x) >> 8) & 0x1f)
252 #define CAP_TX_EP_NUM(x) ((x) & 0x1f)
257 #define VBUS_FRC_EN BIT(0)
262 #define U3D_DEVICE_CONF (SSUSB_EPCTL_CSR_BASE + 0x0000)
263 #define U3D_EP_RST (SSUSB_EPCTL_CSR_BASE + 0x0004)
265 #define U3D_DEV_LINK_INTR_ENABLE (SSUSB_EPCTL_CSR_BASE + 0x0050)
266 #define U3D_DEV_LINK_INTR (SSUSB_EPCTL_CSR_BASE + 0x0054)
272 #define DEV_ADDR(x) ((0x7f & (x)) << 24)
276 #define SSUSB_DEV_SPEED(x) ((x) & 0x7)
281 #define EP_RST(is_in, epnum) (((is_in) ? BIT(16) : BIT(0)) << (epnum))
282 #define EP0_RST BIT(0)
286 #define SSUSB_DEV_SPEED_CHG_INTR BIT(0)
291 #define U3D_LTSSM_CTRL (SSUSB_USB3_MAC_CSR_BASE + 0x0010)
292 #define U3D_USB3_CONFIG (SSUSB_USB3_MAC_CSR_BASE + 0x001C)
294 #define U3D_LINK_STATE_MACHINE (SSUSB_USB3_MAC_CSR_BASE + 0x0134)
295 #define U3D_LTSSM_INTR_ENABLE (SSUSB_USB3_MAC_CSR_BASE + 0x013C)
296 #define U3D_LTSSM_INTR (SSUSB_USB3_MAC_CSR_BASE + 0x0140)
298 #define U3D_U3U2_SWITCH_CTRL (SSUSB_USB3_MAC_CSR_BASE + 0x0170)
307 #define U1_GO_U2_EN BIT(0)
310 #define USB3_EN BIT(0)
313 #define LTSSM_STATE(x) ((x) & 0x1f)
335 #define SS_INACTIVE_INTR BIT(0)
338 #define SOFTCON_CLR_AUTO_EN BIT(0)
342 #define U3D_LINK_UX_INACT_TIMER (SSUSB_USB3_SYS_CSR_BASE + 0x020C)
343 #define U3D_LINK_POWER_CONTROL (SSUSB_USB3_SYS_CSR_BASE + 0x0210)
344 #define U3D_LINK_ERR_COUNT (SSUSB_USB3_SYS_CSR_BASE + 0x0214)
345 #define U3D_DEV_NOTIF_0 (SSUSB_USB3_SYS_CSR_BASE + 0x0290)
346 #define U3D_DEV_NOTIF_1 (SSUSB_USB3_SYS_CSR_BASE + 0x0294)
352 #define DEV_U2_INACT_TIMEOUT_VALUE(x) (((x) & 0xff) << 16)
354 #define U1_INACT_TIMEOUT_MSK GENMASK(7, 0)
355 #define U1_INACT_TIMEOUT_VALUE(x) ((x) & 0xff)
365 #define SW_U1_REQUEST_ENABLE BIT(0)
369 #define LINK_ERROR_COUNT GENMASK(15, 0)
373 #define DEV_NOTIF_VAL_FW(x) (((x) & 0xff) << 8)
374 #define DEV_NOTIF_VAL_LTM(x) (((x) & 0xfff) << 8)
375 #define DEV_NOTIF_VAL_IAM(x) (((x) & 0xffff) << 8)
378 #define TYPE_FUNCTION_WAKE (0x1 << 4)
379 #define TYPE_LATENCY_TOLERANCE_MESSAGE (0x2 << 4)
380 #define TYPE_BUS_INTERVAL_ADJUST_MESSAGE (0x3 << 4)
381 #define TYPE_HOST_ROLE_REQUEST (0x4 << 4)
382 #define TYPE_SUBLINK_SPEED (0x5 << 4)
383 #define SEND_DEV_NOTIF BIT(0)
387 #define U3D_POWER_MANAGEMENT (SSUSB_USB2_CSR_BASE + 0x0004)
388 #define U3D_DEVICE_CONTROL (SSUSB_USB2_CSR_BASE + 0x000C)
389 #define U3D_USB2_TEST_MODE (SSUSB_USB2_CSR_BASE + 0x0014)
390 #define U3D_COMMON_USB_INTR_ENABLE (SSUSB_USB2_CSR_BASE + 0x0018)
391 #define U3D_COMMON_USB_INTR (SSUSB_USB2_CSR_BASE + 0x001C)
392 #define U3D_LINK_RESET_INFO (SSUSB_USB2_CSR_BASE + 0x0024)
393 #define U3D_USB20_FRAME_NUM (SSUSB_USB2_CSR_BASE + 0x003C)
394 #define U3D_USB20_LPM_PARAMETER (SSUSB_USB2_CSR_BASE + 0x0044)
395 #define U3D_USB20_MISC_CONTROL (SSUSB_USB2_CSR_BASE + 0x004C)
396 #define U3D_USB20_OPSTATE (SSUSB_USB2_CSR_BASE + 0x0060)
405 #define LPM_MODE(x) (((x) & 0x3) << 8)
410 #define SUSPENDM_ENABLE BIT(0)
414 #define DC_SESSION BIT(0)
425 #define TEST_SE0_NAK_MODE BIT(0)
436 #define SUSPEND_INTR BIT(0)
442 #define LPM_BESLCK_U3(x) (((x) & 0xf) << 12)
443 #define LPM_BESLCK(x) (((x) & 0xf) << 8)
444 #define LPM_BESLDCK(x) (((x) & 0xf) << 4)
445 #define LPM_BESL GENMASK(3, 0)
448 #define LPM_U3_ACK_EN BIT(0)
452 #define U3D_SSUSB_IP_PW_CTRL0 (SSUSB_SIFSLV_IPPC_BASE + 0x0000)
453 #define U3D_SSUSB_IP_PW_CTRL1 (SSUSB_SIFSLV_IPPC_BASE + 0x0004)
454 #define U3D_SSUSB_IP_PW_CTRL2 (SSUSB_SIFSLV_IPPC_BASE + 0x0008)
455 #define U3D_SSUSB_IP_PW_CTRL3 (SSUSB_SIFSLV_IPPC_BASE + 0x000C)
456 #define U3D_SSUSB_IP_PW_STS1 (SSUSB_SIFSLV_IPPC_BASE + 0x0010)
457 #define U3D_SSUSB_IP_PW_STS2 (SSUSB_SIFSLV_IPPC_BASE + 0x0014)
458 #define U3D_SSUSB_OTG_STS (SSUSB_SIFSLV_IPPC_BASE + 0x0018)
459 #define U3D_SSUSB_OTG_STS_CLR (SSUSB_SIFSLV_IPPC_BASE + 0x001C)
460 #define U3D_SSUSB_IP_XHCI_CAP (SSUSB_SIFSLV_IPPC_BASE + 0x0024)
461 #define U3D_SSUSB_IP_DEV_CAP (SSUSB_SIFSLV_IPPC_BASE + 0x0028)
462 #define U3D_SSUSB_OTG_INT_EN (SSUSB_SIFSLV_IPPC_BASE + 0x002C)
463 #define U3D_SSUSB_U3_CTRL_0P (SSUSB_SIFSLV_IPPC_BASE + 0x0030)
464 #define U3D_SSUSB_U2_CTRL_0P (SSUSB_SIFSLV_IPPC_BASE + 0x0050)
465 #define U3D_SSUSB_REF_CK_CTRL (SSUSB_SIFSLV_IPPC_BASE + 0x008C)
466 #define U3D_SSUSB_DEV_RST_CTRL (SSUSB_SIFSLV_IPPC_BASE + 0x0098)
467 #define U3D_SSUSB_HW_ID (SSUSB_SIFSLV_IPPC_BASE + 0x00A0)
468 #define U3D_SSUSB_HW_SUB_ID (SSUSB_SIFSLV_IPPC_BASE + 0x00A4)
470 #define U3D_SSUSB_PRB_CTRL0 (SSUSB_SIFSLV_IPPC_BASE + 0x00B0)
471 #define U3D_SSUSB_PRB_CTRL1 (SSUSB_SIFSLV_IPPC_BASE + 0x00B4)
472 #define U3D_SSUSB_PRB_CTRL2 (SSUSB_SIFSLV_IPPC_BASE + 0x00B8)
473 #define U3D_SSUSB_PRB_CTRL3 (SSUSB_SIFSLV_IPPC_BASE + 0x00BC)
474 #define U3D_SSUSB_PRB_CTRL4 (SSUSB_SIFSLV_IPPC_BASE + 0x00C0)
475 #define U3D_SSUSB_PRB_CTRL5 (SSUSB_SIFSLV_IPPC_BASE + 0x00C4)
476 #define U3D_SSUSB_IP_SPARE0 (SSUSB_SIFSLV_IPPC_BASE + 0x00C8)
481 #define SSUSB_IP_SW_RST BIT(0)
484 #define SSUSB_IP_HOST_PDN BIT(0)
487 #define SSUSB_IP_DEV_PDN BIT(0)
490 #define SSUSB_IP_PCIE_PDN BIT(0)
498 #define SSUSB_SYSPLL_STABLE BIT(0)
501 #define SSUSB_U2_MAC_SYS_RST_B_STS BIT(0)
510 #define SSUSB_IP_XHCI_U2_PORT_NUM(x) (((x) >> 8) & 0xff)
511 #define SSUSB_IP_XHCI_U3_PORT_NUM(x) ((x) & 0xff)
514 #define SSUSB_IP_DEV_U3_PORT_NUM(x) ((x) & 0xff)
525 #define SSUSB_U3_PORT_DIS BIT(0)
534 #define SSUSB_U2_PORT_DIS BIT(0)
538 #define SSUSB_DEV_SW_RST BIT(0)
541 #define IP_TRUNK_VERS(x) (((x) >> 16) & 0xffff)