142 	csr = mtu3_readl(mbase, U3D_EP0CSR) & EP0_W1C_BITS;  in ep0_stall_set()
147 	mtu3_writel(mtu->mac_base, U3D_EP0CSR, csr);  in ep0_stall_set()
161 	value = mtu3_readl(mbase, U3D_EP0CSR) & EP0_W1C_BITS;  in ep0_do_status_stage()
162 	mtu3_writel(mbase, U3D_EP0CSR, value | EP0_SETUPPKTRDY | EP0_DATAEND);  in ep0_do_status_stage()
314 	readl_poll_timeout_atomic(mbase + U3D_EP0CSR, value,  in handle_test_mode()
520 	csr = mtu3_readl(mbase, U3D_EP0CSR) & EP0_W1C_BITS;  in ep0_rx_state()
554 	mtu3_writel(mbase, U3D_EP0CSR, csr);  in ep0_rx_state()
596 	csr = mtu3_readl(mtu->mac_base, U3D_EP0CSR) & EP0_W1C_BITS;  in ep0_tx_state()
597 	mtu3_writel(mtu->mac_base, U3D_EP0CSR, csr | EP0_TXPKTRDY);  in ep0_tx_state()
600 		mtu3_readl(mtu->mac_base, U3D_EP0CSR));  in ep0_tx_state()
609 	csr = mtu3_readl(mtu->mac_base, U3D_EP0CSR) & EP0_W1C_BITS;  in ep0_read_setup()
627 		mtu3_writel(mtu->mac_base, U3D_EP0CSR,  in ep0_read_setup()
631 		mtu3_writel(mtu->mac_base, U3D_EP0CSR,  in ep0_read_setup()
717 	csr = mtu3_readl(mbase, U3D_EP0CSR);  in mtu3_ep0_isr()
724 		csr = mtu3_readl(mbase, U3D_EP0CSR);  in mtu3_ep0_isr()
746 		mtu3_writel(mbase, U3D_EP0CSR,  in mtu3_ep0_isr()