301 		      ARRAY_SIZE(xhci->run_regs->ir_set));  in xhci_zero_64b_regs()
306 		ir = &xhci->run_regs->ir_set[i];  in xhci_zero_64b_regs()
327 	if (!ir || !ir->ir_set)  in xhci_enable_interrupter()
330 	iman = readl(&ir->ir_set->irq_pending);  in xhci_enable_interrupter()
331 	writel(ER_IRQ_ENABLE(iman), &ir->ir_set->irq_pending);  in xhci_enable_interrupter()
340 	if (!ir || !ir->ir_set)  in xhci_disable_interrupter()
343 	iman = readl(&ir->ir_set->irq_pending);  in xhci_disable_interrupter()
344 	writel(ER_IRQ_DISABLE(iman), &ir->ir_set->irq_pending);  in xhci_disable_interrupter()
355 	if (!ir || !ir->ir_set || imod_interval > U16_MAX * 250)  in xhci_set_interrupter_moderation()
358 	imod = readl(&ir->ir_set->irq_control);  in xhci_set_interrupter_moderation()
361 	writel(imod, &ir->ir_set->irq_control);  in xhci_set_interrupter_moderation()
565 	temp_64 = xhci_read_64(xhci, &ir->ir_set->erst_dequeue);  in xhci_run()
724 		ir->s3_erst_size = readl(&ir->ir_set->erst_size);  in xhci_save_registers()
725 		ir->s3_erst_base = xhci_read_64(xhci, &ir->ir_set->erst_base);  in xhci_save_registers()
726 		ir->s3_erst_dequeue = xhci_read_64(xhci, &ir->ir_set->erst_dequeue);  in xhci_save_registers()
727 		ir->s3_irq_pending = readl(&ir->ir_set->irq_pending);  in xhci_save_registers()
728 		ir->s3_irq_control = readl(&ir->ir_set->irq_control);  in xhci_save_registers()
748 		writel(ir->s3_erst_size, &ir->ir_set->erst_size);  in xhci_restore_registers()
749 		xhci_write_64(xhci, ir->s3_erst_base, &ir->ir_set->erst_base);  in xhci_restore_registers()
750 		xhci_write_64(xhci, ir->s3_erst_dequeue, &ir->ir_set->erst_dequeue);  in xhci_restore_registers()
751 		writel(ir->s3_irq_pending, &ir->ir_set->irq_pending);  in xhci_restore_registers()
752 		writel(ir->s3_irq_control, &ir->ir_set->irq_control);  in xhci_restore_registers()