Lines Matching refs:temp
258 u16 temp; in xhci_common_hub_descriptor() local
263 temp = 0; in xhci_common_hub_descriptor()
266 temp |= HUB_CHAR_INDV_PORT_LPSM; in xhci_common_hub_descriptor()
268 temp |= HUB_CHAR_NO_LPSM; in xhci_common_hub_descriptor()
271 temp |= HUB_CHAR_INDV_PORT_OCPM; in xhci_common_hub_descriptor()
274 desc->wHubCharacteristics = cpu_to_le16(temp); in xhci_common_hub_descriptor()
282 u16 temp; in xhci_usb2_hub_descriptor() local
292 temp = 1 + (ports / 8); in xhci_usb2_hub_descriptor()
293 desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp; in xhci_usb2_hub_descriptor()
649 u32 temp; in xhci_set_port_power() local
652 temp = readl(port->addr); in xhci_set_port_power()
655 hcd->self.busnum, port->hcd_portnum + 1, on ? "ON" : "OFF", temp); in xhci_set_port_power()
657 temp = xhci_port_state_to_neutral(temp); in xhci_set_port_power()
661 writel(temp | PORT_POWER, port->addr); in xhci_set_port_power()
665 writel(temp & ~PORT_POWER, port->addr); in xhci_set_port_power()
669 temp = usb_acpi_power_manageable(hcd->self.root_hub, in xhci_set_port_power()
671 if (temp) in xhci_set_port_power()
680 u32 temp; in xhci_port_set_test_mode() local
685 temp = readl(port->addr + PORTPMSC); in xhci_port_set_test_mode()
686 temp |= test_mode << PORT_TEST_MODE_SHIFT; in xhci_port_set_test_mode()
687 writel(temp, port->addr + PORTPMSC); in xhci_port_set_test_mode()
794 u32 temp; in xhci_set_link_state() local
798 temp = xhci_port_state_to_neutral(portsc); in xhci_set_link_state()
799 temp &= ~PORT_PLS_MASK; in xhci_set_link_state()
800 temp |= PORT_LINK_STROBE | link_state; in xhci_set_link_state()
801 writel(temp, port->addr); in xhci_set_link_state()
805 portsc, temp); in xhci_set_link_state()
811 u32 temp; in xhci_set_remote_wake_mask() local
813 temp = readl(port->addr); in xhci_set_remote_wake_mask()
814 temp = xhci_port_state_to_neutral(temp); in xhci_set_remote_wake_mask()
817 temp |= PORT_WKCONN_E; in xhci_set_remote_wake_mask()
819 temp &= ~PORT_WKCONN_E; in xhci_set_remote_wake_mask()
822 temp |= PORT_WKDISC_E; in xhci_set_remote_wake_mask()
824 temp &= ~PORT_WKDISC_E; in xhci_set_remote_wake_mask()
827 temp |= PORT_WKOC_E; in xhci_set_remote_wake_mask()
829 temp &= ~PORT_WKOC_E; in xhci_set_remote_wake_mask()
831 writel(temp, port->addr); in xhci_set_remote_wake_mask()
838 u32 temp; in xhci_test_and_clear_bit() local
840 temp = readl(port->addr); in xhci_test_and_clear_bit()
841 if (temp & port_bit) { in xhci_test_and_clear_bit()
842 temp = xhci_port_state_to_neutral(temp); in xhci_test_and_clear_bit()
843 temp |= port_bit; in xhci_test_and_clear_bit()
844 writel(temp, port->addr); in xhci_test_and_clear_bit()
1204 u32 temp, status; in xhci_hub_control() local
1259 temp = readl(port->addr); in xhci_hub_control()
1260 if (temp == ~(u32)0) { in xhci_hub_control()
1265 trace_xhci_get_port_status(port, temp); in xhci_hub_control()
1266 status = xhci_get_port_status(hcd, bus_state, wIndex, temp, in xhci_hub_control()
1272 hcd->self.busnum, portnum1, temp, status); in xhci_hub_control()
1285 status = xhci_get_ext_port_status(temp, port_li); in xhci_hub_control()
1305 temp = readl(port->addr); in xhci_hub_control()
1306 if (temp == ~(u32)0) { in xhci_hub_control()
1311 temp = xhci_port_state_to_neutral(temp); in xhci_hub_control()
1315 temp = readl(port->addr); in xhci_hub_control()
1316 if ((temp & PORT_PLS_MASK) != XDEV_U0) { in xhci_hub_control()
1327 temp = readl(port->addr); in xhci_hub_control()
1328 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET) in xhci_hub_control()
1329 || (temp & PORT_PLS_MASK) >= XDEV_U3) { in xhci_hub_control()
1350 temp = readl(port->addr); in xhci_hub_control()
1354 temp = readl(port->addr); in xhci_hub_control()
1359 temp = xhci_port_state_to_neutral(temp); in xhci_hub_control()
1364 temp |= PORT_CSC | PORT_PEC | PORT_WRC | in xhci_hub_control()
1367 writel(temp | PORT_PE, port->addr); in xhci_hub_control()
1368 temp = readl(port->addr); in xhci_hub_control()
1377 temp = readl(port->addr); in xhci_hub_control()
1401 if ((temp & PORT_CONNECT)) { in xhci_hub_control()
1410 temp = readl(port->addr); in xhci_hub_control()
1414 if (!(temp & PORT_PE)) { in xhci_hub_control()
1433 u32 pls = temp & PORT_PLS_MASK; in xhci_hub_control()
1458 temp = readl(port->addr); in xhci_hub_control()
1476 temp = readl(port->addr); in xhci_hub_control()
1477 if ((temp & PORT_PLS_MASK) == XDEV_U3) in xhci_hub_control()
1481 temp = readl(port->addr); in xhci_hub_control()
1495 temp = (temp | PORT_RESET); in xhci_hub_control()
1496 writel(temp, port->addr); in xhci_hub_control()
1498 temp = readl(port->addr); in xhci_hub_control()
1500 hcd->self.busnum, portnum1, temp); in xhci_hub_control()
1504 temp = readl(port->addr); in xhci_hub_control()
1506 hcd->self.busnum, portnum1, temp); in xhci_hub_control()
1509 temp |= PORT_WR; in xhci_hub_control()
1510 writel(temp, port->addr); in xhci_hub_control()
1511 temp = readl(port->addr); in xhci_hub_control()
1516 temp = readl(port->addr + PORTPMSC); in xhci_hub_control()
1517 temp &= ~PORT_U1_TIMEOUT_MASK; in xhci_hub_control()
1518 temp |= PORT_U1_TIMEOUT(timeout); in xhci_hub_control()
1519 writel(temp, port->addr + PORTPMSC); in xhci_hub_control()
1524 temp = readl(port->addr + PORTPMSC); in xhci_hub_control()
1525 temp &= ~PORT_U2_TIMEOUT_MASK; in xhci_hub_control()
1526 temp |= PORT_U2_TIMEOUT(timeout); in xhci_hub_control()
1527 writel(temp, port->addr + PORTPMSC); in xhci_hub_control()
1543 temp = readl(port->addr); in xhci_hub_control()
1552 temp = readl(port->addr); in xhci_hub_control()
1553 if (temp == ~(u32)0) { in xhci_hub_control()
1559 temp = xhci_port_state_to_neutral(temp); in xhci_hub_control()
1562 temp = readl(port->addr); in xhci_hub_control()
1564 xhci_dbg(xhci, "PORTSC %04x\n", temp); in xhci_hub_control()
1565 if (temp & PORT_RESET) in xhci_hub_control()
1567 if ((temp & PORT_PLS_MASK) == XDEV_U3) { in xhci_hub_control()
1568 if ((temp & PORT_PE) == 0) in xhci_hub_control()
1600 port->addr, temp); in xhci_hub_control()
1636 u32 temp, status; in xhci_hub_status_data() local
1678 temp = readl(ports[i]->addr); in xhci_hub_status_data()
1679 if (temp == ~(u32)0) { in xhci_hub_status_data()
1684 trace_xhci_hub_status_data(ports[i], temp); in xhci_hub_status_data()
1686 if ((temp & mask) != 0 || in xhci_hub_status_data()
1693 if ((temp & PORT_RC)) in xhci_hub_status_data()
1695 if (temp & PORT_OC) in xhci_hub_status_data()
1873 u32 temp, portsc; in xhci_bus_resume() local
1892 temp = readl(&xhci->op_regs->command); in xhci_bus_resume()
1893 temp &= ~CMD_EIE; in xhci_bus_resume()
1894 writel(temp, &xhci->op_regs->command); in xhci_bus_resume()
1970 temp = readl(&xhci->op_regs->command); in xhci_bus_resume()
1971 temp |= CMD_EIE; in xhci_bus_resume()
1972 writel(temp, &xhci->op_regs->command); in xhci_bus_resume()
1973 temp = readl(&xhci->op_regs->command); in xhci_bus_resume()