Lines Matching +full:no +full:- +full:tick +full:- +full:in +full:- +full:suspend
1 /* SPDX-License-Identifier: GPL-1.0+ */
6 * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
27 /* first fields are hardware-specified */
41 __hc32 hwNextED; /* next ED in list */
49 struct ed *ed_prev; /* for non-interrupt EDs */
53 /* create --> IDLE --> OPER --> ... --> IDLE --> destroy
54 * usually: OPER --> UNLINK --> (IDLE | OPER) --> ...
69 /* HC may see EDs on rm_list until next frame (frame_no == tick) */
70 u16 tick; member
76 ((int) (ohci->wdh_cnt - ed->takeback_wdh_cnt) >= 0)
80 #define ED_MASK ((u32)~0x0f) /* strip hw status in low addr bits */
89 /* first fields are hardware-specified */
98 /* these two bits are available for definition/use by HCDs in both
112 #define TD_DP_IN 0x00100000 /* IN pid */
117 /* (no hwINFO #defines yet for iso tds) */
124 * big-endian PPC hardware that's the second entry.
132 struct td *td_hash; /* dma-->td hashtable */
142 #define TD_MASK ((u32)~0x1f) /* strip hw status in low addr bits */
145 * Hardware transfer status codes -- CC from td->hwINFO or td->hwPSW
166 /* No Error */ 0,
167 /* CRC Error */ -EILSEQ,
168 /* Bit Stuff */ -EPROTO,
169 /* Data Togg */ -EILSEQ,
170 /* Stall */ -EPIPE,
171 /* DevNotResp */ -ETIME,
172 /* PIDCheck */ -EPROTO,
173 /* UnExpPID */ -EPROTO,
174 /* DataOver */ -EOVERFLOW,
175 /* DataUnder */ -EREMOTEIO,
176 /* (for hw) */ -EIO,
177 /* (for hw) */ -EIO,
178 /* BufferOver */ -ECOMM,
179 /* BuffUnder */ -ENOSR,
180 /* (for HCD) */ -EALREADY,
181 /* (for HCD) */ -EALREADY
188 * told the base address of it. It must be 256-byte aligned.
207 * You must use readl() and writel() (in <asm/io.h>) to access these fields!!
208 * Layout is in section 7 (and appendix B) of the spec.
264 /* pre-shifted values for HCFS */
301 #define RH_PS_PSS 0x00000004 /* port suspend status */
308 #define RH_PS_PSSC 0x00040000 /* port suspend status change */
327 #define RH_A_NPS (1 << 9) /* no power switching */
330 #define RH_A_NOCP (1 << 12) /* no over current protection */
334 /* hcd-private per-urb state */
337 u16 length; // # tds in this request
340 struct td *td[] __counted_by(length); // all TDs in this request
366 * I/O memory used to communicate with the HC (dma-consistent)
371 * main memory used to communicate with the HC (dma-consistent).
380 struct ed *ed_bulktail; /* last in bulk list */
381 struct ed *ed_controltail; /* last in ctrl list */
405 unsigned long next_statechange; /* suspend/resume */
419 #define OHCI_QUIRK_FRAME_NO 0x80 /* no big endian frame_no shift */
422 #define OHCI_QUIRK_AMD_PREFETCH 0x400 /* pre-fetch for ISO transfer */
423 #define OHCI_QUIRK_GLOBAL_SUSPEND 0x800 /* must suspend ports */
426 // there are also chip quirks/bugs in init logic
437 /* platform-specific data -- must come last */
445 return ohci->flags & OHCI_QUIRK_NEC; in quirk_nec()
449 return ohci->flags & OHCI_QUIRK_ZFMICRO; in quirk_zfmicro()
453 return ohci->flags & OHCI_QUIRK_AMD_PLL; in quirk_amdiso()
457 return ohci->flags & OHCI_QUIRK_AMD_PREFETCH; in quirk_amdprefetch()
481 return (struct ohci_hcd *) (hcd->hcd_priv); in hcd_to_ohci()
488 /*-------------------------------------------------------------------------*/
491 dev_dbg (ohci_to_hcd(ohci)->self.controller , fmt , ## args )
493 dev_err (ohci_to_hcd(ohci)->self.controller , fmt , ## args )
495 dev_info (ohci_to_hcd(ohci)->self.controller , fmt , ## args )
497 dev_warn (ohci_to_hcd(ohci)->self.controller , fmt , ## args )
499 /*-------------------------------------------------------------------------*/
503 * in-memory communication descriptors in little-endian format,
505 * processors) implement them in big endian format.
507 * In addition some more exotic implementations like the Toshiba
509 * they have a different endianness for registers vs. in-memory
521 * --------------- ----------------------
530 * (If you have a mixed endian controller, you -must- also define
532 * both your mixed endian and a fully big endian controller support in
538 #define big_endian_desc(ohci) (ohci->flags & OHCI_QUIRK_BE_DESC)
548 #define big_endian_mmio(ohci) (ohci->flags & OHCI_QUIRK_BE_MMIO)
557 * Big-endian read/write functions are arch-specific.
589 /*-------------------------------------------------------------------------*/
649 /*-------------------------------------------------------------------------*/
654 * frame number can wind up in either bits [31:16] (default) or
657 * Somewhat similarly, the 16-bit PSW fields in a transfer descriptor are
665 tmp = be32_to_cpup((__force __be32 *)&ohci->hcca->frame_no); in ohci_frame_no()
666 if (!(ohci->flags & OHCI_QUIRK_FRAME_NO)) in ohci_frame_no()
669 tmp = le32_to_cpup((__force __le32 *)&ohci->hcca->frame_no); in ohci_frame_no()
678 &td->hwPSW[index ^ 1] : &td->hwPSW[index]); in ohci_hwPSWp()
687 /*-------------------------------------------------------------------------*/
689 #define FI 0x2edf /* 12000 bits per frame (-1) */
690 #define FSMP(fi) (0x7fff & ((6 * ((fi) - 210)) / 7))
696 u32 fi = ohci->fminterval & 0x03fff; in periodic_reinit()
697 u32 fit = ohci_readl(ohci, &ohci->regs->fminterval) & FIT; in periodic_reinit()
699 ohci_writel (ohci, (fit ^ FIT) | ohci->fminterval, in periodic_reinit()
700 &ohci->regs->fminterval); in periodic_reinit()
702 &ohci->regs->periodicstart); in periodic_reinit()
705 /* AMD-756 (D2 rev) reports corrupt register contents in some cases.
710 u32 temp = ohci_readl (hc, &hc->regs->roothub.register); \
711 if (temp == -1) \
712 hc->rh_state = OHCI_RH_HALTED; \
713 else if (hc->flags & OHCI_QUIRK_AMD756) \
715 temp = ohci_readl (hc, &hc->regs->roothub.register); \
721 { return ohci_readl (hc, &hc->regs->roothub.b); } in roothub_b()
723 { return ohci_readl (hc, &hc->regs->roothub.status); } in roothub_status()