usb/host/ehci.h

1 /* SPDX-License-Identifier: GPL-2.0+ */
3  * Copyright (c) 2001-2002 by David Brownell
16  * To facilitate the strongest possible byte-order checking from "sparse"
46  * high-speed devices and full/low-speed devices lying behind a TT.
53 	u16			cs_mask;	/* C-mask and S-mask bytes */
66 /* ehci_hcd->lock guards shared data against other CPUs:
92  * ehci-timer.c) in parallel with this list.
188 			the change-suspend feature turned on */
194 	/* per-HC memory pools (could be per-bus, but ...) */
236 	unsigned		has_ppcd:1; /* support per-port change bits */
261 	/* platform-specific data -- must come last */
268 	return (struct ehci_hcd *) (hcd->hcd_priv);  in hcd_to_ehci()
275 /*-------------------------------------------------------------------------*/
279 /*-------------------------------------------------------------------------*/
286  * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
306 #define	QTD_STS_MMF	(1 << 2)	/* incomplete split transaction */
307 #define	QTD_STS_STS	(1 << 1)	/* split transaction state */
317 	/* the rest is HCD-private */
324 /* PID Codes that are used here, from EHCI specification, Table 3-16. */
329 /* mask NakCnt+T in qh->hw_alt_next */
335 /*-------------------------------------------------------------------------*/
337 /* type tag from {qh,itd,sitd,fstn}->hw_next */
344  * can be used on one system with SoC EHCI controller using big-endian
345  * descriptors as well as a normal little-endian PCI EHCI controller.
377 /*-------------------------------------------------------------------------*/
382  * See Fig 3-7 "Queue Head Structure Layout".
397 #define	QH_INACTIVATE	(1 << 7)	/* Inactivate on next transaction */
404 	__hc32			hw_current;	/* qtd list - see EHCI 3.6.4 */
416 	/* the rest is HCD-private */
448 	unsigned		clearing_tt:1;	/* Clear-TT-Buf in progress */
453 /*-------------------------------------------------------------------------*/
455 /* description of one iso transaction (up to 3 KB data if highspeed) */
458 	u64			bufp;		/* itd->hw_bufp{,_hi}[pg] |= */
459 	__hc32			transaction;	/* itd->hw_transaction[i] |= */  member
466  * each packet is one logical usb transaction to the device (not TT),
467  * beginning at stream->next_uframe
477  * ehci_iso_stream - groups all (s)itds for this endpoint.
510 /*-------------------------------------------------------------------------*/
514  * Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
525 #define EHCI_ISOC_XACTERR       (1<<28)        /* XactErr - transaction error */
534 	/* the rest is HCD-private */
545 	unsigned		index[8];	/* in urb->iso_frame_desc */
548 /*-------------------------------------------------------------------------*/
552  * siTD, aka split-transaction isochronous Transfer Descriptor
554  * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD)
559 /* uses bit field macros above - see EHCI 0.95 Table 3-8 */
560 	__hc32			hw_fullspeed_ep;	/* EHCI table 3-9 */
561 	__hc32			hw_uframe;		/* EHCI table 3-10 */
562 	__hc32			hw_results;		/* EHCI table 3-11 */
571 #define	SITD_STS_MMF	(1 << 2)	/* incomplete split transaction */
572 #define	SITD_STS_STS	(1 << 1)	/* split transaction state */
576 	__hc32			hw_buf[2];		/* EHCI table 3-12 */
577 	__hc32			hw_backpointer;		/* EHCI table 3-13 */
580 	/* the rest is HCD-private */
591 /*-------------------------------------------------------------------------*/
606 	/* the rest is HCD-private */
611 /*-------------------------------------------------------------------------*/
614  * USB-2.0 Specification Sections 11.14 and 11.18
617  * A hub can have a single TT for all its ports, or multiple TTs (one for each
618  * port).  The bandwidth and budgeting information for the full/low-speed bus
619  * below each TT is self-contained and independent of the other TTs or the
620  * high-speed bus.
624  * the best-case estimate of the number of full-speed bytes allocated to an
628  * keep an up-to-date record, we recompute the budget when it is needed.
640 /*-------------------------------------------------------------------------*/
650 /*-------------------------------------------------------------------------*/
655  * Some EHCI controllers have a Transaction Translator built into the
656  * root hub. This is a non-standard feature.  Each controller will need
661 #define	ehci_is_TDI(e)			(ehci_to_hcd(e)->has_tt)
668 		switch ((portsc >> (ehci->has_hostpc ? 25 : 26)) & 3) {  in ehci_port_speed()
688 /*-------------------------------------------------------------------------*/
692  * port number in the queue head was 0..N-1 instead of 1..N.
694 #define	ehci_has_fsl_portno_bug(e)		((e)->has_fsl_port_bug)
699 #define PORTSC_FSL_PFSC	24	/* Port Force Full-Speed Connect */
702 /* Some Freescale processors have an erratum (USB A-005275) in which
705 #define ehci_has_fsl_hs_errata(e)	((e)->has_fsl_hs_errata)
711  * Some Freescale/NXP processors have an erratum (USB A-005697)
715 #define ehci_has_fsl_susp_errata(e)	((e)->has_fsl_susp_errata)
723 	((e)->has_ci_pec_bug && ((e)->command & CMD_PSE) \
728  * little-endian format, a minority (celleb companion chip) implement
737  * as fields of a 32-bit register.
741 #define ehci_big_endian_mmio(e)		((e)->big_endian_mmio)
742 #define ehci_big_endian_capbase(e)	((e)->big_endian_capbase)
749  * Big-endian read/write functions are arch-specific.
789 	if (ehci->imx28_write_fix)  in ehci_writel()
797  * On certain ppc-44x SoC there is a HW issue, that could only worked around with
806 	hc_control = (readl_be(ehci->ohci_hcctrl_reg) & ~OHCI_CTRL_HCFS);  in set_ohci_hcfs()
812 	writel_be(hc_control, ehci->ohci_hcctrl_reg);  in set_ohci_hcfs()
813 	(void) readl_be(ehci->ohci_hcctrl_reg);  in set_ohci_hcfs()
820 /*-------------------------------------------------------------------------*/
823  * The AMCC 440EPx not only implements its EHCI registers in big-endian
826  * EHCI controllers accessed through PCI work normally (little-endian
827  * everywhere), so we won't bother supporting a BE-only mode for now.
830 #define ehci_big_endian_desc(e)		((e)->big_endian_desc)
876 /*-------------------------------------------------------------------------*/
879 	dev_dbg(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
881 	dev_err(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
883 	dev_info(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
885 	dev_warn(ehci_to_hcd(ehci)->self.controller, fmt, ## args)
887 /*-------------------------------------------------------------------------*/