Lines Matching +full:0 +full:x00008000
16 #define EP_DIR_OUT 0
18 #define DMA_ADDR_INVALID (~(dma_addr_t)0)
22 #define WAIT_FOR_SETUP 0
28 #define CAPLENGTH_MASK (0xff)
29 #define DCCPARAMS_DEN_MASK (0x1f)
31 #define HCSPARAMS_PPC (0x10)
34 #define USB_FRINDEX_MASKS 0x3fff
37 #define USBCMD_RUN_STOP (0x00000001)
38 #define USBCMD_CTRL_RESET (0x00000002)
39 #define USBCMD_SETUP_TRIPWIRE_SET (0x00002000)
42 #define USBCMD_ATDTW_TRIPWIRE_SET (0x00004000)
46 #define USBCMD_FRAME_SIZE_1024 (0x00000000) /* 000 */
47 #define USBCMD_FRAME_SIZE_512 (0x00000004) /* 001 */
48 #define USBCMD_FRAME_SIZE_256 (0x00000008) /* 010 */
49 #define USBCMD_FRAME_SIZE_128 (0x0000000C) /* 011 */
50 #define USBCMD_FRAME_SIZE_64 (0x00008000) /* 100 */
51 #define USBCMD_FRAME_SIZE_32 (0x00008004) /* 101 */
52 #define USBCMD_FRAME_SIZE_16 (0x00008008) /* 110 */
53 #define USBCMD_FRAME_SIZE_8 (0x0000800C) /* 111 */
55 #define EPCTRL_TX_ALL_MASK (0xFFFF0000)
56 #define EPCTRL_RX_ALL_MASK (0x0000FFFF)
58 #define EPCTRL_TX_DATA_TOGGLE_RST (0x00400000)
59 #define EPCTRL_TX_EP_STALL (0x00010000)
60 #define EPCTRL_RX_EP_STALL (0x00000001)
61 #define EPCTRL_RX_DATA_TOGGLE_RST (0x00000040)
62 #define EPCTRL_RX_ENABLE (0x00000080)
63 #define EPCTRL_TX_ENABLE (0x00800000)
64 #define EPCTRL_CONTROL (0x00000000)
65 #define EPCTRL_ISOCHRONOUS (0x00040000)
66 #define EPCTRL_BULK (0x00080000)
67 #define EPCTRL_INT (0x000C0000)
68 #define EPCTRL_TX_TYPE (0x000C0000)
69 #define EPCTRL_RX_TYPE (0x0000000C)
70 #define EPCTRL_DATA_TOGGLE_INHIBIT (0x00000020)
77 #define USB_EP_LIST_ADDRESS_MASK 0xfffff800
79 #define PORTSCX_W1C_BITS 0x2a
80 #define PORTSCX_PORT_RESET 0x00000100
81 #define PORTSCX_PORT_POWER 0x00001000
82 #define PORTSCX_FORCE_FULL_SPEED_CONNECT 0x01000000
83 #define PORTSCX_PAR_XCVR_SELECT 0xC0000000
84 #define PORTSCX_PORT_FORCE_RESUME 0x00000040
85 #define PORTSCX_PORT_SUSPEND 0x00000080
86 #define PORTSCX_PORT_SPEED_FULL 0x00000000
87 #define PORTSCX_PORT_SPEED_LOW 0x04000000
88 #define PORTSCX_PORT_SPEED_HIGH 0x08000000
89 #define PORTSCX_PORT_SPEED_MASK 0x0C000000
92 #define USBMODE_CTRL_MODE_IDLE 0x00000000
93 #define USBMODE_CTRL_MODE_DEVICE 0x00000002
94 #define USBMODE_CTRL_MODE_HOST 0x00000003
95 #define USBMODE_CTRL_MODE_RSV 0x00000001
96 #define USBMODE_SETUP_LOCK_OFF 0x00000008
97 #define USBMODE_STREAM_DISABLE 0x00000010
100 #define USBSTS_INT 0x00000001
101 #define USBSTS_ERR 0x00000002
102 #define USBSTS_PORT_CHANGE 0x00000004
103 #define USBSTS_FRM_LST_ROLL 0x00000008
104 #define USBSTS_SYS_ERR 0x00000010
105 #define USBSTS_IAA 0x00000020
106 #define USBSTS_RESET 0x00000040
107 #define USBSTS_SOF 0x00000080
108 #define USBSTS_SUSPEND 0x00000100
109 #define USBSTS_HC_HALTED 0x00001000
110 #define USBSTS_RCL 0x00002000
111 #define USBSTS_PERIODIC_SCHEDULE 0x00004000
112 #define USBSTS_ASYNC_SCHEDULE 0x00008000
116 #define USBINTR_INT_EN (0x00000001)
117 #define USBINTR_ERR_INT_EN (0x00000002)
118 #define USBINTR_PORT_CHANGE_DETECT_EN (0x00000004)
120 #define USBINTR_ASYNC_ADV_AAE (0x00000020)
121 #define USBINTR_ASYNC_ADV_AAE_ENABLE (0x00000020)
122 #define USBINTR_ASYNC_ADV_AAE_DISABLE (0xFFFFFFDF)
124 #define USBINTR_RESET_EN (0x00000040)
125 #define USBINTR_SOF_UFRAME_EN (0x00000080)
126 #define USBINTR_DEVICE_SUSPEND (0x00000100)
128 #define USB_DEVICE_ADDRESS_MASK (0xfe000000)
163 u32 epctrlx[16]; /* Endpoint Control, where x = 0.. 15 */
250 #define EP_QUEUE_HEAD_ZLT_SEL 0x20000000
252 #define EP_QUEUE_HEAD_MAX_PKT_LEN(ep_info) (((ep_info)>>16)&0x07ff)
253 #define EP_QUEUE_HEAD_IOS 0x00008000
254 #define EP_QUEUE_HEAD_NEXT_TERMINATE 0x00000001
255 #define EP_QUEUE_HEAD_IOC 0x00008000
256 #define EP_QUEUE_HEAD_MULTO 0x00000C00
257 #define EP_QUEUE_HEAD_STATUS_HALT 0x00000040
258 #define EP_QUEUE_HEAD_STATUS_ACTIVE 0x00000080
259 #define EP_QUEUE_CURRENT_OFFSET_MASK 0x00000FFF
260 #define EP_QUEUE_HEAD_NEXT_POINTER_MASK 0xFFFFFFE0
261 #define EP_QUEUE_FRINDEX_MASK 0x000007FF
262 #define EP_MAX_LENGTH_TRANSFER 0x4000
269 /* Total bytes (16..30), IOC (15), INT (8), STS (0-7) */
271 u32 buff_ptr0; /* Buffer pointer Page 0 (12-31) */
283 #define DTD_NEXT_TERMINATE (0x00000001)
284 #define DTD_IOC (0x00008000)
285 #define DTD_STATUS_ACTIVE (0x00000080)
286 #define DTD_STATUS_HALTED (0x00000040)
287 #define DTD_STATUS_DATA_BUFF_ERR (0x00000020)
288 #define DTD_STATUS_TRANSACTION_ERR (0x00000008)
289 #define DTD_RESERVED_FIELDS (0x00007F00)
290 #define DTD_ERROR_MASK (0x68)
291 #define DTD_ADDR_MASK (0xFFFFFFE0)
292 #define DTD_PACKET_SIZE 0x7FFF0000
298 u32 buff_ptr0; /* Buffer pointer Page 0 */