Lines Matching full:csr
111 u32 csr; in proc_ep_show() local
118 csr = __raw_readl(ep->creg); in proc_ep_show()
131 seq_printf(s, "csr %08x rxbytes=%d %s %s %s" EIGHTBITS "\n", in proc_ep_show()
132 csr, in proc_ep_show()
133 (csr & 0x07ff0000) >> 16, in proc_ep_show()
134 (csr & (1 << 15)) ? "enabled" : "disabled", in proc_ep_show()
135 (csr & (1 << 11)) ? "DATA1" : "DATA0", in proc_ep_show()
136 types[(csr & 0x700) >> 8], in proc_ep_show()
139 (!(csr & 0x700)) in proc_ep_show()
140 ? ((csr & (1 << 7)) ? " IN" : " OUT") in proc_ep_show()
142 (csr & (1 << 6)) ? " rxdatabk1" : "", in proc_ep_show()
143 (csr & (1 << 5)) ? " forcestall" : "", in proc_ep_show()
144 (csr & (1 << 4)) ? " txpktrdy" : "", in proc_ep_show()
146 (csr & (1 << 3)) ? " stallsent" : "", in proc_ep_show()
147 (csr & (1 << 2)) ? " rxsetup" : "", in proc_ep_show()
148 (csr & (1 << 1)) ? " rxdatabk0" : "", in proc_ep_show()
149 (csr & (1 << 0)) ? " txcomp" : ""); in proc_ep_show()
289 * Endpoint FIFO CSR bits have a mix of bits, making it unsafe to just write
314 u32 csr; in read_fifo() local
326 csr = __raw_readl(creg); in read_fifo()
327 if ((csr & RX_DATA_READY) == 0) in read_fifo()
330 count = (csr & AT91_UDP_RXBYTECNT) >> 16; in read_fifo()
341 csr |= CLR_FX; in read_fifo()
344 csr &= ~(SET_FX | AT91_UDP_RX_DATA_BK0); in read_fifo()
347 csr &= ~(SET_FX | AT91_UDP_RX_DATA_BK1); in read_fifo()
351 csr &= ~(SET_FX | AT91_UDP_RX_DATA_BK0); in read_fifo()
352 __raw_writel(csr, creg); in read_fifo()
371 * CSR returns bad RXCOUNT when read too soon after updating in read_fifo()
374 csr = __raw_readl(creg); in read_fifo()
388 u32 csr = __raw_readl(creg); in write_fifo() local
405 if (unlikely(csr & (AT91_UDP_TXCOMP | AT91_UDP_TXPKTRDY))) { in write_fifo()
406 if (csr & AT91_UDP_TXCOMP) { in write_fifo()
407 csr |= CLR_FX; in write_fifo()
408 csr &= ~(SET_FX | AT91_UDP_TXCOMP); in write_fifo()
409 __raw_writel(csr, creg); in write_fifo()
410 csr = __raw_readl(creg); in write_fifo()
412 if (csr & AT91_UDP_TXPKTRDY) in write_fifo()
441 csr &= ~SET_FX; in write_fifo()
442 csr |= CLR_FX | AT91_UDP_TXPKTRDY; in write_fifo()
443 __raw_writel(csr, creg); in write_fifo()
741 u32 csr; in at91_ep_set_halt() local
751 csr = __raw_readl(creg); in at91_ep_set_halt()
758 if (ep->is_in && (!list_empty(&ep->queue) || (csr >> 16) != 0)) in at91_ep_set_halt()
761 csr |= CLR_FX; in at91_ep_set_halt()
762 csr &= ~SET_FX; in at91_ep_set_halt()
764 csr |= AT91_UDP_FORCESTALL; in at91_ep_set_halt()
769 csr &= ~AT91_UDP_FORCESTALL; in at91_ep_set_halt()
771 __raw_writel(csr, creg); in at91_ep_set_halt()
1009 u32 csr = __raw_readl(creg); in handle_ep() local
1018 if (csr & (AT91_UDP_STALLSENT | AT91_UDP_TXCOMP)) { in handle_ep()
1019 csr |= CLR_FX; in handle_ep()
1020 csr &= ~(SET_FX | AT91_UDP_STALLSENT | AT91_UDP_TXCOMP); in handle_ep()
1021 __raw_writel(csr, creg); in handle_ep()
1027 if (csr & AT91_UDP_STALLSENT) { in handle_ep()
1031 csr |= CLR_FX; in handle_ep()
1032 csr &= ~(SET_FX | AT91_UDP_STALLSENT); in handle_ep()
1033 __raw_writel(csr, creg); in handle_ep()
1034 csr = __raw_readl(creg); in handle_ep()
1036 if (req && (csr & RX_DATA_READY)) in handle_ep()
1047 static void handle_setup(struct at91_udc *udc, struct at91_ep *ep, u32 csr) in handle_setup() argument
1057 rxcount = (csr & AT91_UDP_RXBYTECNT) >> 16; in handle_setup()
1062 csr |= AT91_UDP_DIR; in handle_setup()
1065 csr &= ~AT91_UDP_DIR; in handle_setup()
1070 ERR("SETUP len %d, csr %08x\n", rxcount, csr); in handle_setup()
1073 csr |= CLR_FX; in handle_setup()
1074 csr &= ~(SET_FX | AT91_UDP_RXSETUP); in handle_setup()
1075 __raw_writel(csr, creg); in handle_setup()
1095 csr = __raw_readl(creg); in handle_setup()
1096 csr |= CLR_FX; in handle_setup()
1097 csr &= ~SET_FX; in handle_setup()
1102 __raw_writel(csr | AT91_UDP_TXPKTRDY, creg); in handle_setup()
1258 csr |= AT91_UDP_FORCESTALL; in handle_setup()
1259 __raw_writel(csr, creg); in handle_setup()
1268 csr |= AT91_UDP_TXPKTRDY; in handle_setup()
1269 __raw_writel(csr, creg); in handle_setup()
1277 u32 csr = __raw_readl(creg); in handle_ep0() local
1280 if (unlikely(csr & AT91_UDP_STALLSENT)) { in handle_ep0()
1283 csr |= CLR_FX; in handle_ep0()
1284 csr &= ~(SET_FX | AT91_UDP_STALLSENT | AT91_UDP_FORCESTALL); in handle_ep0()
1285 __raw_writel(csr, creg); in handle_ep0()
1287 csr = __raw_readl(creg); in handle_ep0()
1289 if (csr & AT91_UDP_RXSETUP) { in handle_ep0()
1292 handle_setup(udc, ep0, csr); in handle_ep0()
1302 if (csr & AT91_UDP_TXCOMP) { in handle_ep0()
1303 csr |= CLR_FX; in handle_ep0()
1304 csr &= ~(SET_FX | AT91_UDP_TXCOMP); in handle_ep0()
1321 __raw_writel(csr, creg); in handle_ep0()
1345 else if (csr & AT91_UDP_RX_DATA_BK0) { in handle_ep0()
1346 csr |= CLR_FX; in handle_ep0()
1347 csr &= ~(SET_FX | AT91_UDP_RX_DATA_BK0); in handle_ep0()
1355 csr = __raw_readl(creg); in handle_ep0()
1356 csr &= ~SET_FX; in handle_ep0()
1357 csr |= CLR_FX | AT91_UDP_TXPKTRDY; in handle_ep0()
1358 __raw_writel(csr, creg); in handle_ep0()
1380 __raw_writel(csr | AT91_UDP_FORCESTALL, creg); in handle_ep0()
1387 __raw_writel(csr, creg); in handle_ep0()