Lines Matching refs:AST_UDC_EP0_CTRL
45 #define AST_UDC_EP0_CTRL 0x30 /* Endpoint 0 Control/Status Register */ macro
605 ast_udc_write(udc, EP0_TX_LEN(tx_len), AST_UDC_EP0_CTRL); in ast_udc_ep0_queue()
607 AST_UDC_EP0_CTRL); in ast_udc_ep0_queue()
619 ast_udc_write(udc, EP0_TX_BUFF_RDY, AST_UDC_EP0_CTRL); in ast_udc_ep0_queue()
622 ast_udc_write(udc, EP0_RX_BUFF_RDY, AST_UDC_EP0_CTRL); in ast_udc_ep0_queue()
736 ctrl = ast_udc_read(udc, AST_UDC_EP0_CTRL); in ast_udc_ep_set_halt()
742 ast_udc_write(udc, ctrl, AST_UDC_EP0_CTRL); in ast_udc_ep_set_halt()
777 ast_udc_write(udc, EP0_RX_BUFF_RDY, AST_UDC_EP0_CTRL); in ast_udc_ep0_rx()
783 ast_udc_write(udc, EP0_TX_BUFF_RDY, AST_UDC_EP0_CTRL); in ast_udc_ep0_tx()
798 rx_len = EP0_GET_RX_LEN(ast_udc_read(udc, AST_UDC_EP0_CTRL)); in ast_udc_ep0_out()
985 ast_udc_write(udc, EP0_TX_LEN(len), AST_UDC_EP0_CTRL); in ast_udc_ep0_data_tx()
987 AST_UDC_EP0_CTRL); in ast_udc_ep0_data_tx()
991 ast_udc_write(udc, EP0_TX_BUFF_RDY, AST_UDC_EP0_CTRL); in ast_udc_ep0_data_tx()
1028 ast_udc_write(udc, ast_udc_read(udc, AST_UDC_EP0_CTRL) | EP0_STALL, in ast_udc_getstatus()
1029 AST_UDC_EP0_CTRL); in ast_udc_getstatus()
1112 ast_udc_write(udc, ast_udc_read(udc, AST_UDC_EP0_CTRL) | EP0_STALL, in ast_udc_ep0_handle_setup()
1113 AST_UDC_EP0_CTRL); in ast_udc_ep0_handle_setup()
1118 ast_udc_write(udc, EP0_TX_BUFF_RDY, AST_UDC_EP0_CTRL); in ast_udc_ep0_handle_setup()
1434 ast_udc_write(udc, 0, AST_UDC_EP0_CTRL); in ast_udc_init_hw()