gadget/udc/amd5536udc.h

1 // SPDX-License-Identifier: GPL-2.0+
3  * amd5536.h -- header for AMD 5536 UDC high/full speed USB device controller
56 /* Global CSR's -------------------------------------------------------------*/
59 /* EP NE bits */
79 /* max pkt */
83 /* Device Config Register ---------------------------------------------------*/
106 /* Device Control Register --------------------------------------------------*/
130 /* Device Status Register ---------------------------------------------------*/
157 /* Device Interrupt Register ------------------------------------------------*/
169 /* Device Interrupt Mask Register -------------------------------------------*/
174 /* Endpoint Interrupt Register ----------------------------------------------*/
193 /* Endpoint Interrupt Mask Register -----------------------------------------*/
202 /* mask non-EP0 endpoints */
207 /* Endpoint-specific CSR's --------------------------------------------------*/
231 /* Endpoint Status Registers ------------------------------------------------*/
250 /* Endpoint Buffer Size IN/ Receive Packet Frame Number OUT Registers ------*/
261 /* fifo size mult = fifo size / max packet */
275 /* Endpoint Buffer Size OUT/Max Packet Size Registers -----------------------*/
283 /* EP0in max packet size = 64 bytes */
285 /* EP0out max packet size = 64 bytes */
287 /* EP0in fullspeed max packet size = 64 bytes */
289 /* EP0out fullspeed max packet size = 64 bytes */
293  * Endpoint dma descriptors ------------------------------------------------
341 /* max ep0in packet */
343 /* max dma packet */
346 /* un-usable DMA address */
349 /* other Endpoint register addresses and values-----------------------------*/
361 /* UDC CSR regs are aligned but AHB regs not - offset for OUT EP's */
367 /* Rx fifo address and size = 1k -------------------------------------------*/
371 /* Tx fifo address and size = 1.5k -----------------------------------------*/
375 /* default data endpoints --------------------------------------------------*/
380 /* general constants -------------------------------------------------------*/
386 /*---------------------------------------------------------------------------*/
390 	/* sca - setup command address */
434 	/* endpoint buffer size out/max packet size */
457 	/* first setup word */
459 	/* second setup word */
600 /* packet per buffer dma */
602 /* with per descr. update */
611 MODULE_PARM_DESC(use_dma_ppb, "true for DMA in packet per buffer mode");
614 	"true for DMA in packet per buffer mode with descriptor update");
618  *---------------------------------------------------------------------------
633  * set bitfield value in zero-initialized u32 u32Val
634  * => bitfield bits in u32Val are all zero
646 /* SET and GET bits in u32 values ------------------------------------------*/
651 /* debug macros ------------------------------------------------------------*/
653 #define DBG(udc , args...)	dev_dbg(udc->dev, args)