3  * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
209 	/* we share one TRB for ep0/1 */  in dwc3_gadget_ep0_queue()
232 	/* stall is always issued on EP0 */  in dwc3_ep0_stall_and_restart()
865 	struct dwc3_ep		*ep0;  in dwc3_ep0_complete_data()  local
872 	ep0 = dwc->eps[0];  in dwc3_ep0_complete_data()
876 	trace_dwc3_complete_trb(ep0, trb);  in dwc3_ep0_complete_data()
878 	r = next_request(&ep0->pending_list);  in dwc3_ep0_complete_data()
886 			dwc3_gadget_giveback(ep0, r, -ECONNRESET);  in dwc3_ep0_complete_data()
897 	if ((IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) &&  in dwc3_ep0_complete_data()
901 		trace_dwc3_complete_trb(ep0, trb);  in dwc3_ep0_complete_data()
914 		dwc3_gadget_giveback(ep0, r, 0);  in dwc3_ep0_complete_data()
1112 	 * For status/DATA OUT stage, TRB will be queued on ep0 out  in dwc3_ep0_end_control_data()
1114 	 * queuing ENDXFER command for ep0 out endpoint.  in dwc3_ep0_end_control_data()