1 // SPDX-License-Identifier: GPL-2.0
3  * dwc3-of-simple.c - OF glue layer for simple integrations
5  * Copyright (c) 2015 Texas Instruments Incorporated - https://www.ti.com
9  * This is a combination of the old dwc3-qcom.c by Ivan T. Ivanov
10  * <iivanov@mm-sol.com> and the original patch adding support for Xilinx' SoC
18 #include <linux/dma-mapping.h>
29 	struct reset_control	*resets;  member
36 	struct device		*dev = &pdev->dev;  in dwc3_of_simple_probe()
37 	struct device_node	*np = dev->of_node;  in dwc3_of_simple_probe()
43 		return -ENOMEM;  in dwc3_of_simple_probe()
46 	simple->dev = dev;  in dwc3_of_simple_probe()
49 	 * Some controllers need to toggle the usb3-otg reset before trying to  in dwc3_of_simple_probe()
52 	if (of_device_is_compatible(np, "rockchip,rk3399-dwc3"))  in dwc3_of_simple_probe()
53 		simple->need_reset = true;  in dwc3_of_simple_probe()
55 	simple->resets = of_reset_control_array_get_optional_exclusive(np);  in dwc3_of_simple_probe()
56 	if (IS_ERR(simple->resets)) {  in dwc3_of_simple_probe()
57 		ret = PTR_ERR(simple->resets);  in dwc3_of_simple_probe()
58 		dev_err(dev, "failed to get device resets, err=%d\n", ret);  in dwc3_of_simple_probe()
62 	ret = reset_control_deassert(simple->resets);  in dwc3_of_simple_probe()
66 	ret = clk_bulk_get_all(simple->dev, &simple->clks);  in dwc3_of_simple_probe()
70 	simple->num_clocks = ret;  in dwc3_of_simple_probe()
71 	ret = clk_bulk_prepare_enable(simple->num_clocks, simple->clks);  in dwc3_of_simple_probe()
86 	clk_bulk_disable_unprepare(simple->num_clocks, simple->clks);  in dwc3_of_simple_probe()
87 	clk_bulk_put_all(simple->num_clocks, simple->clks);  in dwc3_of_simple_probe()
90 	reset_control_assert(simple->resets);  in dwc3_of_simple_probe()
93 	reset_control_put(simple->resets);  in dwc3_of_simple_probe()
99 	of_platform_depopulate(simple->dev);  in __dwc3_of_simple_teardown()
101 	clk_bulk_disable_unprepare(simple->num_clocks, simple->clks);  in __dwc3_of_simple_teardown()
102 	clk_bulk_put_all(simple->num_clocks, simple->clks);  in __dwc3_of_simple_teardown()
103 	simple->num_clocks = 0;  in __dwc3_of_simple_teardown()
105 	reset_control_assert(simple->resets);  in __dwc3_of_simple_teardown()
107 	reset_control_put(simple->resets);  in __dwc3_of_simple_teardown()
109 	pm_runtime_disable(simple->dev);  in __dwc3_of_simple_teardown()
110 	pm_runtime_put_noidle(simple->dev);  in __dwc3_of_simple_teardown()
111 	pm_runtime_set_suspended(simple->dev);  in __dwc3_of_simple_teardown()
132 	clk_bulk_disable(simple->num_clocks, simple->clks);  in dwc3_of_simple_runtime_suspend()
141 	return clk_bulk_enable(simple->num_clocks, simple->clks);  in dwc3_of_simple_runtime_resume()
148 	if (simple->need_reset)  in dwc3_of_simple_suspend()
149 		reset_control_assert(simple->resets);  in dwc3_of_simple_suspend()
158 	if (simple->need_reset)  in dwc3_of_simple_resume()
159 		reset_control_deassert(simple->resets);  in dwc3_of_simple_resume()
171 	{ .compatible = "rockchip,rk3399-dwc3" },
172 	{ .compatible = "sprd,sc9860-dwc3" },
173 	{ .compatible = "allwinner,sun50i-h6-dwc3" },
174 	{ .compatible = "hisilicon,hi3670-dwc3" },
175 	{ .compatible = "hisilicon,hi3798mv200-dwc3" },
176 	{ .compatible = "intel,keembay-dwc3" },
186 		.name	= "dwc3-of-simple",