1 // SPDX-License-Identifier: GPL-2.0
5  * Copyright (C) 2010-2017 Cavium Networks
24 /* BIST fast-clear mode select. A BIST run with this bit set
30 /* Reference clock select for SuperSpeed and HighSpeed PLLs:
31  *	0x0 = Both PLLs use DLMC_REF_CLK0 for reference clock
32  *	0x1 = Both PLLs use DLMC_REF_CLK1 for reference clock
33  *	0x2 = SuperSpeed PLL uses DLMC_REF_CLK0 for reference clock &
34  *	      HighSpeed PLL uses PLL_REF_CLK for reference clck
35  *	0x3 = SuperSpeed PLL uses DLMC_REF_CLK1 for reference clock &
36  *	      HighSpeed PLL uses PLL_REF_CLK for reference clck
39 /* 1 = Spread-spectrum clock enable, 0 = SS clock disable */
41 /* Spread-spectrum clock modulation range:
42  *	0x0 = -4980 ppm downspread
43  *	0x1 = -4492 ppm downspread
44  *	0x2 = -4003 ppm downspread
45  *	0x3 - 0x7 = Reserved
48 /* Enable non-standard oscillator frequencies:
49  *	[55:53] = modules -1
53 /* Reference clock multiplier for non-standard frequencies:
60 /* Enable reference clock to prescaler for SuperSpeed functionality.
64 /* Divide the reference clock by 2 before entering the
72 /* Select reference clock freqnuency for both PLL blocks:
79 /* Select bypass input to controller clock divider:
86 /* Clock divider select:
136 /* Bus-master enable: 0x0 = Disabled (stall DMAs), 0x1 = enabled */
141  *	0x0 = Overcurrent indication from off-chip is active-low
142  *	0x1 = Overcurrent indication from off-chip is active-high
148  *	0x0 = Port power to off-chip is active-low
149  *	0x1 = Port power to off-chip is active-high
157 /* Out-of-bound UAHC register access: 0 = read, 1 = write */
159 /* SRCID error log for out-of-bound UAHC register access:
161  *	[57] = Request source: 0 = core, 1 = NCB-device
162  *	[56:51] = Core/NCB-device number, [56] always 0 for NCB devices
170 /* Select the IOI read command used by DMA accesses */
172 /* Select endian format for DMA accesses to the L2C:
179 /* Select endian format for IOI CSR access to UAHC:
195 #define DWC3_GPIO_POWER_NONE	(-1)
260 	return -EINVAL;  in dwc3_octeon_get_divider()
269 	struct device *dev = octeon->dev;  in dwc3_octeon_setup()
270 	void __iomem *uctl_ctl_reg = octeon->base + USBDRD_UCTL_CTL;  in dwc3_octeon_setup()
271 	void __iomem *uctl_host_cfg_reg = octeon->base + USBDRD_UCTL_HOST_CFG;  in dwc3_octeon_setup()
278 	/* Step 2: Select GPIO for overcurrent indication, if desired. SKIP */  in dwc3_octeon_setup()
292 	/* Step 4b: Select controller clock frequency. */  in dwc3_octeon_setup()
307 		return -EINVAL;  in dwc3_octeon_setup()
314 	/* Step 5a: Reference clock configuration. */  in dwc3_octeon_setup()
326 	/* Step 5b: Configure and enable spread-spectrum for SuperSpeed. */  in dwc3_octeon_setup()
339 	/* Step 7: Wait 10 controller-clock cycles to take effect. */  in dwc3_octeon_setup()
347 	/* Step 8b: Wait 10 controller-clock cycles. */  in dwc3_octeon_setup()
357 		dwc3_octeon_config_gpio(((__force uintptr_t)octeon->base >> 24) & 1,  in dwc3_octeon_setup()
372 	/* Step 8e: Wait 10 controller-clock cycles. */  in dwc3_octeon_setup()
391 	void __iomem *uctl_shim_cfg_reg = octeon->base + USBDRD_UCTL_SHIM_CFG;  in dwc3_octeon_set_endian_mode()
406 	void __iomem *uctl_ctl_reg = octeon->base + USBDRD_UCTL_CTL;  in dwc3_octeon_phy_reset()
415 	struct device *dev = &pdev->dev;  in dwc3_octeon_probe()
416 	struct device_node *node = dev->of_node;  in dwc3_octeon_probe()
424 	if (of_property_read_u32(node, "refclk-frequency", &clock_rate)) {  in dwc3_octeon_probe()
425 		dev_err(dev, "No UCTL \"refclk-frequency\"\n");  in dwc3_octeon_probe()
426 		return -EINVAL;  in dwc3_octeon_probe()
428 	if (of_property_read_string(node, "refclk-type-ss", &ss_clock_type)) {  in dwc3_octeon_probe()
429 		dev_err(dev, "No UCTL \"refclk-type-ss\"\n");  in dwc3_octeon_probe()
430 		return -EINVAL;  in dwc3_octeon_probe()
432 	if (of_property_read_string(node, "refclk-type-hs", &hs_clock_type)) {  in dwc3_octeon_probe()
433 		dev_err(dev, "No UCTL \"refclk-type-hs\"\n");  in dwc3_octeon_probe()
434 		return -EINVAL;  in dwc3_octeon_probe()
488 		return -ENOMEM;  in dwc3_octeon_probe()
490 	octeon->dev = dev;  in dwc3_octeon_probe()
491 	octeon->base = devm_platform_ioremap_resource(pdev, 0);  in dwc3_octeon_probe()
492 	if (IS_ERR(octeon->base))  in dwc3_octeon_probe()
493 		return PTR_ERR(octeon->base);  in dwc3_octeon_probe()
512 	of_platform_depopulate(octeon->dev);  in dwc3_octeon_remove()
516 	{ .compatible = "cavium,octeon-7130-usb-uctl" },
525 		.name	= "dwc3-octeon",
531 MODULE_ALIAS("platform:dwc3-octeon");
532 MODULE_AUTHOR("Ladislav Michl <ladis@linux-mips.org>");