usb/dwc3/dwc3-octeon.c

1 // SPDX-License-Identifier: GPL-2.0
5  * Copyright (C) 2010-2017 Cavium Networks
24 /* BIST fast-clear mode select. A BIST run with this bit set
39 /* 1 = Spread-spectrum clock enable, 0 = SS clock disable */
41 /* Spread-spectrum clock modulation range:
42  *	0x0 = -4980 ppm downspread
43  *	0x1 = -4492 ppm downspread
44  *	0x2 = -4003 ppm downspread
45  *	0x3 - 0x7 = Reserved
48 /* Enable non-standard oscillator frequencies:
49  *	[55:53] = modules -1
53 /* Reference clock multiplier for non-standard frequencies:
54  *	0x19 = 100MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1
55  *	0x28 = 125MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1
56  *	0x32 =  50MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1
84 /* Reset controller clock divider. */
97 /* USB3 port permanently attached: 0x0 = No, 0x1 = Yes */
99 /* USB2 port permanently attached: 0x0 = No, 0x1 = Yes */
101 /* Disable SuperSpeed PHY: 0x0 = No, 0x1 = Yes */
103 /* Disable HighSpeed PHY: 0x0 = No, 0x1 = Yes */
105 /* Enable PHY SuperSpeed block power: 0x0 = No, 0x1 = Yes */
107 /* Enable PHY HighSpeed block power: 0x0 = No, 0x1 = Yes */
109 /* Enable USB UCTL interface clock: 0xx = No, 0x1 = Yes */
113 /* PHY reset */
115 /* Software reset UAHC */
136 /* Bus-master enable: 0x0 = Disabled (stall DMAs), 0x1 = enabled */
141  *	0x0 = Overcurrent indication from off-chip is active-low
142  *	0x1 = Overcurrent indication from off-chip is active-high
145 /* Port power control enable: 0x0 = unavailable, 0x1 = available */
147 /* Port power control sense selection:
148  *	0x0 = Port power to off-chip is active-low
149  *	0x1 = Port power to off-chip is active-high
157 /* Out-of-bound UAHC register access: 0 = read, 1 = write */
159 /* SRCID error log for out-of-bound UAHC register access:
161  *	[57] = Request source: 0 = core, 1 = NCB-device
162  *	[56:51] = Core/NCB-device number, [56] always 0 for NCB devices
195 #define DWC3_GPIO_POWER_NONE	(-1)
260 	return -EINVAL;  in dwc3_octeon_get_divider()
269 	struct device *dev = octeon->dev;  in dwc3_octeon_setup()
270 	void __iomem *uctl_ctl_reg = octeon->base + USBDRD_UCTL_CTL;  in dwc3_octeon_setup()
271 	void __iomem *uctl_host_cfg_reg = octeon->base + USBDRD_UCTL_HOST_CFG;  in dwc3_octeon_setup()
287 	/* Step 4a: Reset the clock dividers. */  in dwc3_octeon_setup()
307 		return -EINVAL;  in dwc3_octeon_setup()
310 	/* Step 4c: Deassert the controller clock divider reset. */  in dwc3_octeon_setup()
326 	/* Step 5b: Configure and enable spread-spectrum for SuperSpeed. */  in dwc3_octeon_setup()
334 	/* Step 6a & 6b: Power up PHYs. */  in dwc3_octeon_setup()
339 	/* Step 7: Wait 10 controller-clock cycles to take effect. */  in dwc3_octeon_setup()
342 	/* Step 8a: Deassert UCTL reset signal. */  in dwc3_octeon_setup()
347 	/* Step 8b: Wait 10 controller-clock cycles. */  in dwc3_octeon_setup()
350 	/* Step 8c: Setup power control. */  in dwc3_octeon_setup()
357 		dwc3_octeon_config_gpio(((__force uintptr_t)octeon->base >> 24) & 1,  in dwc3_octeon_setup()
359 		dev_dbg(dev, "power control is using gpio%d\n", power_gpio);  in dwc3_octeon_setup()
367 	/* Step 8d: Deassert UAHC reset signal. */  in dwc3_octeon_setup()
372 	/* Step 8e: Wait 10 controller-clock cycles. */  in dwc3_octeon_setup()
391 	void __iomem *uctl_shim_cfg_reg = octeon->base + USBDRD_UCTL_SHIM_CFG;  in dwc3_octeon_set_endian_mode()
406 	void __iomem *uctl_ctl_reg = octeon->base + USBDRD_UCTL_CTL;  in dwc3_octeon_phy_reset()
415 	struct device *dev = &pdev->dev;  in dwc3_octeon_probe()
416 	struct device_node *node = dev->of_node;  in dwc3_octeon_probe()
424 	if (of_property_read_u32(node, "refclk-frequency", &clock_rate)) {  in dwc3_octeon_probe()
425 		dev_err(dev, "No UCTL \"refclk-frequency\"\n");  in dwc3_octeon_probe()
426 		return -EINVAL;  in dwc3_octeon_probe()
428 	if (of_property_read_string(node, "refclk-type-ss", &ss_clock_type)) {  in dwc3_octeon_probe()
429 		dev_err(dev, "No UCTL \"refclk-type-ss\"\n");  in dwc3_octeon_probe()
430 		return -EINVAL;  in dwc3_octeon_probe()
432 	if (of_property_read_string(node, "refclk-type-hs", &hs_clock_type)) {  in dwc3_octeon_probe()
433 		dev_err(dev, "No UCTL \"refclk-type-hs\"\n");  in dwc3_octeon_probe()
434 		return -EINVAL;  in dwc3_octeon_probe()
479 	len = of_property_read_variable_u32_array(node, "power", gpio_pwr, 2, 3);  in dwc3_octeon_probe()
488 		return -ENOMEM;  in dwc3_octeon_probe()
490 	octeon->dev = dev;  in dwc3_octeon_probe()
491 	octeon->base = devm_platform_ioremap_resource(pdev, 0);  in dwc3_octeon_probe()
492 	if (IS_ERR(octeon->base))  in dwc3_octeon_probe()
493 		return PTR_ERR(octeon->base);  in dwc3_octeon_probe()
512 	of_platform_depopulate(octeon->dev);  in dwc3_octeon_remove()
516 	{ .compatible = "cavium,octeon-7130-usb-uctl" },
525 		.name	= "dwc3-octeon",
531 MODULE_ALIAS("platform:dwc3-octeon");
532 MODULE_AUTHOR("Ladislav Michl <ladis@linux-mips.org>");